Subversion Repositories socgen

assign  txd_break_n  = !txd_break ;

   
   
always@(posedge clk)
  if(reset)            rts_pad_out  <= 1'b0;
  else                 rts_pad_out  <= rts_in;

always@(posedge clk)
  if(reset)            cts_out      <= 1'b0;
  else                 cts_out      <= cts_pad_in;

   



generate

if(DIV == 0)
  begin   
assign    baud_clk_div = baud_clk;
  end
else   
begin
cde_divider_def
#(.SIZE(DIV_SIZE))  
baud_divider  (
         .clk             ( clk          ),
         .reset           ( reset        ),
         .divider_in      ( divider_in   ),
         .enable          ( baud_clk     ),
         .divider_out     ( baud_clk_div )
         );
end  

endgenerate










   

always@(posedge clk)
  if(reset)
    begin
       xmit_start     <= 1'b0;
    end
  else
  if( !fifo_empty &&   cde_buffer_empty &&  !xmit_start )  
    begin
       xmit_start     <= 1'b1;
    end
  else
    begin
       xmit_start     <= 1'b0;
    end

assign txd_buffer_empty =      !fifo_full;

assign fifo_pop =  !fifo_empty &&   cde_buffer_empty && ! xmit_start;