Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--
//                                                                        //
// Author : John Eaton  Ouabache Designworks                              //
//                                                                        //
//   Copyright (C) 2010 Authors and OPENCORES.ORG                         //
//                                                                        //
//   This source file may be used and distributed without                 //
//   restriction provided that this copyright statement is not            //
//   removed from the file and that any derivative work contains          //
//   the original copyright notice and the associated disclaimer.         //
//                                                                        //
//   This source file is free software; you can redistribute it           //
//   and/or modify it under the terms of the GNU Lesser General           //
//   Public License as published by the Free Software Foundation;         //
//   either version 2.1 of the License, or (at your option) any           //
//   later version.                                                       //
//                                                                        //
//   This source is distributed in the hope that it will be               //
//   useful, but WITHOUT ANY WARRANTY; without even the implied           //
//   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR              //
//   PURPOSE. See the GNU Lesser General Public License for more          //
//   details.                                                             //
//                                                                        //
//   You should have received a copy of the GNU Lesser General            //
//   Public License along with this source; if not, download it           //
//   from http://www.opencores.org/lgpl.shtml                             //
//                                                                        //
-->
<spirit:design 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>logic</spirit:library>
<spirit:name>vga_char_ctrl</spirit:name>
<spirit:version>def.design</spirit:version>  











<spirit:vendorExtensions><socgen:nodes>


<socgen:node><spirit:name>pixel_count</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>10</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>


<socgen:node><spirit:name>line_count</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>9</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>


<socgen:node><spirit:name>subchar_pixel</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>2</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>

<socgen:node><spirit:name>subchar_line</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>2</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>


<socgen:node><spirit:name>char_column</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>6</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>


<socgen:node><spirit:name>char_line</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>6</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>






<socgen:node><spirit:name>cursor_on</spirit:name>
<spirit:typeName>reg</spirit:typeName>

</socgen:node>



<socgen:node><spirit:name>char_read_addr</spirit:name>
<spirit:typeName>wire</spirit:typeName>
<spirit:wire>
<spirit:vector><spirit:left>13</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</socgen:node>




</socgen:nodes></spirit:vendorExtensions>





<spirit:adHocConnections>


     <spirit:adHocConnection>
       <spirit:name>clk</spirit:name>
       <spirit:externalPortReference spirit:portRef="slave_clk_clk"/>
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="clk"/>
     </spirit:adHocConnection>


     <spirit:adHocConnection>
       <spirit:name>address</spirit:name>
       <spirit:externalPortReference spirit:portRef="address" spirit:left="12" spirit:right="0"   />
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="waddr"/>
     </spirit:adHocConnection>

     <spirit:adHocConnection>
       <spirit:name>char_read_addr</spirit:name>
       <spirit:externalPortReference spirit:portRef="char_read_addr" spirit:left="12" spirit:right="0"  />
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="raddr"/>
     </spirit:adHocConnection>


     <spirit:adHocConnection>
       <spirit:name>ascii_load</spirit:name>
       <spirit:externalPortReference spirit:portRef="ascii_load"/>
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="wr"/>
     </spirit:adHocConnection>


     <spirit:adHocConnection>
       <spirit:name>wdata</spirit:name>
       <spirit:externalPortReference spirit:portRef="wdata" spirit:left="7" spirit:right="0"  />
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="wdata"/>
     </spirit:adHocConnection>

     <spirit:adHocConnection>
       <spirit:name>ascii_code</spirit:name>
       <spirit:externalPortReference spirit:portRef="ascii_code" spirit:left="7" spirit:right="0"  />
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="rdata"/>
     </spirit:adHocConnection>


     <spirit:adHocConnection  spirit:tiedValue="1'b1">
        <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="cs"/>
       <spirit:internalPortReference spirit:componentRef="char_ram"   spirit:portRef="rd"/>
     </spirit:adHocConnection>



</spirit:adHocConnections>



















<spirit:componentInstances>

<spirit:componentInstance>
<spirit:instanceName>char_ram</spirit:instanceName> <spirit:componentRef spirit:vendor="opencores.org" spirit:library="cde" spirit:name="sram" spirit:version="dp" />

<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="ADDR">CHAR_RAM_ADDR</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WIDTH">CHAR_RAM_WIDTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WORDS">CHAR_RAM_WORDS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="WRITETHRU">CHAR_RAM_WRITETHRU</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="DEFAULT">CHAR_RAM_DEFAULT</spirit:configurableElementValue>
</spirit:configurableElementValues>
 </spirit:componentInstance>


</spirit:componentInstances>


</spirit:design>