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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [doc/] [Heda/] [absDef/] [wb_b.1_rtl.txt] - Rev 131

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opencores.org:wishbone:wb:b.1_rtl
        --------------------------------------------------------------------------------------------------------
        Filename:  ./projects/opencores.org/wishbone/busDefs/abstractors/wb_b.1_rtl.xml
        VLNV-ad     opencores.org_wishbone_wb_b.1_rtl
        VLNV-bt     opencores.org_wishbone_wb_b.1
             SystemGroup Name CLOCK 
             SystemGroup Name RESET 
             SystemGroup Name ENABLE 

Port:  clk   CLOCK  Requires Driver  clock    
  onMaster presence    required 
  onMaster width       1 
  onMaster direction   in 

  onSlave  presence    required 
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Port:  enable       
  onMaster presence    optional 
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Port:  rst   RESET  Requires Driver  singleShot    
  onMaster presence    required 
  onMaster width       1 
  onMaster direction   in 

  onSlave  presence    required 
  onSlave  width       1 
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Port:  adr       
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Port:  cyc       
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Port:  wdata       
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Port:  rdata       
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Port:  ack       
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Port:  err       
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Port:  rty       
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Port:  sel       
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Port:  stb       
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Port:  tagn_i       
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Port:  tagn_o       
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Port:  we       
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