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opencores.org:wishbone:wishbone:rtl
        --------------------------------------------------------------------------------------------------------
        Filename:  ./projects/opencores.org/wishbone/busDefs/abstractors/wishbone_rtl.xml
        VLNV-ad     opencores.org_wishbone_wishbone_rtl
        VLNV-bt     opencores.org_wishbone_wishbone_def
             SystemGroup Name CLOCK 
             SystemGroup Name RESET 
             SystemGroup Name CLOCKEN 

Port:  clk   CLOCK  Requires Driver  clock    

Port:  reset_n   RESET  Requires Driver  singleShot    

Port:  reset       Default Value   1  

Port:  clk_en       Default Value   1  

Port:  wdata       

Port:  rdata       

Port:  wtgd       

Port:  rtgd       

Port:  ack       

Port:  adr       

Port:  cyc       

Port:  stall       

Port:  cab       

Port:  err       

Port:  lock       

Port:  rty       

Port:  sel       

Port:  stb       

Port:  tga       

Port:  tgc       

Port:  cti       

Port:  bte       

Port:  we