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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_memory/] [rtl/] [verilog/] [top.body] - Rev 131

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reg waitst;
 
 
   always @ (posedge clk_i or posedge rst_i)
     if (rst_i)                  waitst <= 1'b0;
     else
     if (!ack_o) 
       begin
        if (cyc_i & stb_i)       waitst <= 1'b1;
        else                     waitst <= waitst;
       end
     else                        waitst <= 1'b0;




   // ack_o
   always @ (posedge clk_i or posedge rst_i)
     if (rst_i)                             ack_o <= 1'b0;
     else
     if (!ack_o) 
       begin
        if (cyc_i & stb_i & waitst )        ack_o <= 1'b1; 
        else                                ack_o <= ack_o; 
       end
     else                                   ack_o <= 1'b0;




assign sram_wr        =   we_i & ack_o;




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