URL
https://opencores.org/ocsvn/socgen/socgen/trunk
Subversion Repositories socgen
[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [wishbone/] [ip/] [wb_uart16550/] [rtl/] [verilog/] [top.body] - Rev 131
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wire [7:0] rb_dll_rdata;
wire [7:0] ie_dlh_rdata;
wire [7:0] tr_reg_wdata;
wire [3:0] ie_reg_wdata;
wire [15:0] dl_reg_wdata;
wire [7:0] scratch;
wire [3:0] ier;
wire [3:0] iir;
wire [7:0] fcr;
wire [4:0] mcr;
wire [7:0] lcr;
wire [7:0] msr;
wire [7:0] lsr;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire we_o;
wire re_o;
wire tr_reg_wr;
wire rb_dll_reg_dec;
wire ls_reg_dec;
wire ms_reg_dec;
wire ii_reg_dec;
wire ie_reg_wr;
`VARIANT`WB_FSM wb_interface
(
.clk ( wb_clk_i ),
.wb_rst_i ( wb_rst_i ),
.wb_we_i ( wb_we_i ),
.wb_stb_i ( wb_stb_i ),
.wb_cyc_i ( wb_cyc_i ),
.wb_ack_o ( wb_ack_o ),
.we_o ( we_o ),
.re_o ( re_o )
);
`VARIANT`WB
#(.LC_REG_RST(8'b00000011),
.II_REG_PAD(4'b1100),
.FC_REG_RST(8'b11000000)
)
micro_reg (
.clk ( wb_clk_i ),
.reset ( wb_rst_i ),
.enable (1'b1 ),
.cs ( wb_cyc_i ),
.wr ( wb_we_i ),
.rd (~wb_we_i ),
.addr ( wb_adr_i ),
.byte_lanes ( wb_sel_i ),
.wdata ( wb_dat_i ),
.rdata ( wb_dat_o ),
.rb_dll_reg_rdata ( rb_dll_rdata ),
.rb_dll_reg_dec ( rb_dll_reg_dec ),
.tr_reg_wr_0 ( tr_reg_wr ),
.tr_reg_wdata ( tr_reg_wdata ),
.dll_reg_wdata ( dl_reg_wdata[7:0] ),
.dlh_reg_wdata ( dl_reg_wdata[15:8] ),
.ls_reg_dec ( ls_reg_dec ),
.ms_reg_dec ( ms_reg_dec ),
.ii_reg_dec ( ii_reg_dec ),
.ie_dlh_reg_rdata ( ie_dlh_rdata ),
.ie_reg_wr_0 ( ie_reg_wr ),
.ie_reg_wdata ( ie_reg_wdata ),
.ii_reg_rdata ( iir ),
.fc_reg ( fcr ),
.next_fc_reg ( {fcr[7:6],6'h00} ),
.lc_reg ( lcr ),
.lc_reg_rdata ( lcr ),
.next_lc_reg ( lcr ),
.mc_reg ( mcr ),
.mc_reg_rdata ( mcr ),
.next_mc_reg ( mcr ),
.ls_reg_rdata ( lsr ),
.ms_reg_rdata ( msr ),
.sr_reg ( scratch ),
.sr_reg_rdata ( scratch ),
.next_sr_reg ( scratch ),
.rb_dll_reg_cs ( ),
.tr_reg_cs ( ),
.tr_reg_dec ( ),
.ie_dlh_reg_cs ( ),
.ie_dlh_reg_dec ( ),
.ie_reg_cs ( ),
.ie_reg_dec ( ),
.dll_reg_cs ( ),
.dll_reg_dec ( ),
.dll_reg_wr_0 ( ),
.dlh_reg_cs ( ),
.dlh_reg_dec ( ),
.dlh_reg_wr_0 ( ),
.ii_reg_cs ( ),
.fc_reg_cs ( ),
.fc_reg_dec ( ),
.fc_reg_wr_0 ( ),
.lc_reg_cs ( ),
.lc_reg_dec ( ),
.lc_reg_wr_0 ( ),
.mc_reg_cs ( ),
.mc_reg_dec ( ),
.mc_reg_wr_0 ( ),
.ls_reg_cs ( ),
.ms_reg_cs ( ),
.sr_reg_cs ( ),
.sr_reg_dec ( ),
.sr_reg_wr_0 ( ),
.debug_0_reg_cs ( ),
.debug_0_reg_dec ( ),
.debug_1_reg_cs ( ),
.debug_1_reg_dec ( ),
.debug_0_reg_rdata ({msr,lcr,iir,ier,lsr}),
.debug_1_reg_rdata ({8'b0, fcr[7:6],mcr, rf_count, rstate, tf_count, tstate})
);
`VARIANT`REGS
#(.PRESCALER_PRESET(PRESCALER_PRESET))
regs
(
.clk ( wb_clk_i ),
.wb_rst_i ( wb_rst_i ),
.wb_we_i ( we_o ),
.wb_re_i ( re_o ),
.wb_dat_i ( dl_reg_wdata ),
.tr_reg_wr ( tr_reg_wr ),
.tr_reg_wdata ( tr_reg_wdata ),
.rb_dll_reg_rd ( rb_dll_reg_dec ),
.rdata_rb_dll ( rb_dll_rdata ),
.rdata_ie_dlh ( ie_dlh_rdata ),
.ls_reg_rd ( ls_reg_dec ),
.ms_reg_rd ( ms_reg_dec ),
.ii_reg_rd ( ii_reg_dec ),
.ie_reg_wr ( ie_reg_wr ),
.ie_reg_wdata ( ie_reg_wdata ),
.cts_pad_i ( cts_pad_i ),
.dsr_pad_i ( dsr_pad_i ),
.ri_pad_i ( ri_pad_i ),
.dcd_pad_i ( dcd_pad_i ),
.stx_pad_o ( stx_pad_o ),
.srx_pad_i ( srx_pad_i ),
.ier ( ier ),
.iir ( iir ),
.fcr ( fcr ),
.lcr ( lcr ),
.msr ( msr ),
.lsr ( lsr ),
.mcr ( mcr ),
.rf_count ( rf_count ),
.tf_count ( tf_count ),
.tstate ( tstate ),
.rstate ( rstate ),
.rts_pad_o ( rts_pad_o ),
.dtr_pad_o ( dtr_pad_o ),
.int_o ( int_o ),
.baud_o ( baud_o )
);