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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [bfms/] [clock_gen/] [sim/] [testbenches/] [xml/] [clock_gen_bfm.design.xml] - Rev 131
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<?xml version="1.0" encoding="UTF-8"?>
<!--
// //
// Author : John Eaton Ouabache Designworks //
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
-->
<spirit:design
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>Testbench</spirit:library>
<spirit:name>clock_gen</spirit:name>
<spirit:version>bfm.design</spirit:version>
<spirit:vendorExtensions>
<socgen:nodes>
<socgen:node>
<spirit:name>STOP</spirit:name>
<spirit:typeName>wire</spirit:typeName>
</socgen:node>
<socgen:node>
<spirit:name>BAD</spirit:name>
<spirit:typeName>wire</spirit:typeName>
</socgen:node>
</socgen:nodes>
</spirit:vendorExtensions>
<spirit:adHocConnections>
<spirit:adHocConnection>
<spirit:name>clk</spirit:name>
<spirit:externalPortReference spirit:portRef="clk"/>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="clk"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>reset</spirit:name>
<spirit:externalPortReference spirit:portRef="reset"/>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="reset"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>START</spirit:name>
<spirit:externalPortReference spirit:portRef="START"/>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="START"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>FAIL</spirit:name>
<spirit:externalPortReference spirit:portRef="FAIL"/>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="FAIL"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>FINISH</spirit:name>
<spirit:externalPortReference spirit:portRef="FINISH"/>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="FINISH"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>STOP</spirit:name>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="STOP"/>
</spirit:adHocConnection>
<spirit:adHocConnection>
<spirit:name>BAD</spirit:name>
<spirit:internalPortReference spirit:componentRef="cg" spirit:portRef="BAD"/>
</spirit:adHocConnection>
</spirit:adHocConnections>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>cg</spirit:instanceName>
<spirit:componentRef spirit:vendor="opencores.org" spirit:library="Testbench" spirit:name="clock_gen" spirit:version="def" />
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>
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