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https://opencores.org/ocsvn/socgen/socgen/trunk
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[/] [socgen/] [trunk/] [common/] [opencores.org/] [Testbench/] [doc/] [sch/] [clock_gen_def.sch] - Rev 135
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v 20100214 1
C 2200 300 1 0 0 in_port_vector.sym
{
T 2200 300 5 10 1 1 0 6 1 1
refdes=STOP[STOP_WIDTH-1:0]
}
C 2200 700 1 0 0 in_port_vector.sym
{
T 2200 700 5 10 1 1 0 6 1 1
refdes=BAD[BAD_WIDTH-1:0]
}
C 2200 1100 1 0 0 in_port.sym
{
T 2200 1100 5 10 1 1 0 6 1 1
refdes=clk
}
C 2200 1500 1 0 0 in_port.sym
{
T 2200 1500 5 10 1 1 0 6 1 1
refdes=START
}
C 4100 300 1 0 0 out_port.sym
{
T 5100 300 5 10 1 1 0 0 1 1
refdes=reset
}
C 4100 700 1 0 0 out_port.sym
{
T 5100 700 5 10 1 1 0 0 1 1
refdes=FINISH
}
C 4100 1100 1 0 0 out_port.sym
{
T 5100 1100 5 10 1 1 0 0 1 1
refdes=FAIL
}