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<h1><a name="Datasheet"></a>SOCGEN Datasheet:<br>
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<ul>
  <li>
    <ul>
      <li>
        <p style="margin-bottom: 0in;"><a href="#TheoryofOperation">Theory of Operation<br>
        </a></p>
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<h2><b><a name="TheoryofOperation"></a>Theory of Operation<br></b></h2>
The cde_clock_gater provides a means to gate a clock from a synchronized enable signal.<br>
 
The cde_clock_gater will latch the enable signal during the clock low period so that the next rising edge can immediately propagate to the output. This gating is disabled when the atg_clk_mode signal is active. A scan observation flop may be added to this module to test the enable signal(s)<br>
 
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<img style="width: 533px; height: 182px;" alt=""  src="../png/cde_clock_gater.png"><br> 
 
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