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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [clock/] [rtl/] [verilog/] [clock_testmux.v] - Rev 131
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/**********************************************************************/ /* */ /* */ /* Copyright (c) 2012 Ouabache Design Works */ /* */ /* All Rights Reserved Worldwide */ /* */ /* Licensed under the Apache License,Version2.0 (the'License'); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in */ /* writing, software distributed under the License is */ /* distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES */ /* OR CONDITIONS OF ANY KIND, either express or implied. */ /* See the License for the specific language governing */ /* permissions and limitations under the License. */ /**********************************************************************/ module cde_clock_testmux ( input wire sel, input wire clk_0, input wire clk_1, output wire clk_out ); assign clk_out = (clk_1 && sel) || (clk_0 && (!sel)) || (clk_1 && clk_0); endmodule