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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_rpc_reg.xml] - Rev 131

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<?xml version="1.0" encoding="UTF-8"?>
<!--

-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>jtag</spirit:name>
<spirit:version>rpc_reg</spirit:version>  <spirit:configuration>default</spirit:configuration>  


<spirit:componentGenerators>







</spirit:componentGenerators>



<spirit:fileSets>

   <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

 
      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../verilog/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

  </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../verilog/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>



   </spirit:fileSet>


    <spirit:fileSet>

      <spirit:name>fs-lint</spirit:name>
      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName><spirit:name>../verilog/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

    </spirit:fileSet>




</spirit:fileSets>





<spirit:model>    
       <spirit:views>





              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>



              <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>






      </spirit:views>



<spirit:modelParameters>
<spirit:modelParameter><spirit:name>BITS</spirit:name><spirit:value>16</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>RESET_VALUE</spirit:name><spirit:value>'h0</spirit:value></spirit:modelParameter>
</spirit:modelParameters>

<spirit:ports>

<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>reset</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>tdi</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>select</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>update_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>capture_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>shift_dr</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>tdo</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>capture_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>update_value</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>BITS-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>




</spirit:ports>

</spirit:model>    










</spirit:component>

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