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[/] [socgen/] [trunk/] [common/] [opencores.org/] [cde/] [ip/] [jtag/] [sim/] [testbenches/] [verilog/] [tb.rpc_2] - Rev 131
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reg [JTAG_USER2_WIDTH-1:0] rpc_2_reg;always @(posedge clk or posedge reset)beginif(reset) rpc_2_reg <= JTAG_USER2_RESET;else rpc_2_reg <= rpc_2_reg;endassign rpc_2_wire = rpc_2_reg;