Subversion Repositories socgen

<?xml version="1.0" encoding="UTF-8"?>
<!--

-->
<spirit:component 
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">

<spirit:vendor>opencores.org</spirit:vendor>
<spirit:library>cde</spirit:library>
<spirit:name>sync</spirit:name>
<spirit:version>with_reset</spirit:version>  <spirit:configuration>default</spirit:configuration>  




<spirit:componentGenerators>




<spirit:componentGenerator>
  <spirit:name>gen_verilog</spirit:name>
  <spirit:phase>104.0</spirit:phase>
  <spirit:apiType>none</spirit:apiType>
  <spirit:vendorExtensions><socgen:envIdentifier>common</socgen:envIdentifier></spirit:vendorExtensions>
  <spirit:generatorExe>./tools/verilog/gen_verilog</spirit:generatorExe>
  <spirit:parameters>
    <spirit:parameter> 
      <spirit:name>destination</spirit:name>
      <spirit:value>sync_with_reset</spirit:value>
    </spirit:parameter>
  </spirit:parameters>
</spirit:componentGenerator>




</spirit:componentGenerators>



<spirit:model>    

   <spirit:views>


            <spirit:view>
              <spirit:name>verilog</spirit:name>              
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="verilog"/> 
              </spirit:vendorExtensions>
              </spirit:view>






              <spirit:view>
              <spirit:name>common</spirit:name><spirit:envIdentifier>common</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-common</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>



              <spirit:view>
              <spirit:name>sim</spirit:name><spirit:envIdentifier>:*Simulation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-sim</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>

              <spirit:view>
              <spirit:name>syn</spirit:name><spirit:envIdentifier>:*Synthesis:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              <spirit:modelName></spirit:modelName>
                     <spirit:fileSetRef>
                            <spirit:localName>fs-syn</spirit:localName>
                     </spirit:fileSetRef>
              </spirit:view>







       <spirit:view>
              <spirit:name>doc</spirit:name>
              <spirit:vendorExtensions>
              <spirit:componentRef spirit:vendor="opencores.org" 
                                   spirit:library="Testbench" 
                                   spirit:name="toolflow" 
                                   spirit:version="documentation"/> 
              </spirit:vendorExtensions>
              <spirit:envIdentifier>:*Documentation:*</spirit:envIdentifier>
              <spirit:language>Verilog</spirit:language>
              </spirit:view>




    </spirit:views>

<spirit:modelParameters>
<spirit:modelParameter><spirit:name>WIDTH</spirit:name><spirit:value>1</spirit:value></spirit:modelParameter>
<spirit:modelParameter><spirit:name>DEPTH</spirit:name><spirit:value>2</spirit:value></spirit:modelParameter>
</spirit:modelParameters>

<spirit:ports>

<spirit:port><spirit:name>clk</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>reset_n</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction></spirit:wire>
</spirit:port>


<spirit:port><spirit:name>data_in</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>in</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>

<spirit:port><spirit:name>data_out</spirit:name>
<spirit:wireTypeDefs><spirit:wireTypeDef><spirit:typeName>wire</spirit:typeName></spirit:wireTypeDef></spirit:wireTypeDefs>
<spirit:wire><spirit:direction>out</spirit:direction>
<spirit:vector><spirit:left>WIDTH-1</spirit:left><spirit:right>0</spirit:right></spirit:vector></spirit:wire>
</spirit:port>




</spirit:ports>

</spirit:model>    




<spirit:fileSets>



   <spirit:fileSet>
      <spirit:name>fs-common</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/sync_with_reset</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>fragment</spirit:userFileType>
      </spirit:file>





   </spirit:fileSet>



   <spirit:fileSet>
      <spirit:name>fs-sim</spirit:name>

 
      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/sync_with_reset</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>

      <spirit:file>
      <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/sim/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

  </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-syn</spirit:name>

      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/copyright</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>include</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName></spirit:logicalName>
        <spirit:name>../verilog/common/sync_with_reset</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType><spirit:userFileType>module</spirit:userFileType>
      </spirit:file>


      <spirit:file>
        <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/syn/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>



   </spirit:fileSet>


   <spirit:fileSet>
      <spirit:name>fs-lint</spirit:name>

      <spirit:file>
      <spirit:logicalName>dest_dir</spirit:logicalName>
        <spirit:name>../views/syn/</spirit:name>
        <spirit:fileType>verilogSource</spirit:fileType>
        <spirit:userFileType>libraryDir</spirit:userFileType>
      </spirit:file>

   </spirit:fileSet>




</spirit:fileSets>










</spirit:component>