Subversion Repositories sockit_owm

#!/bin/bash
 
# cleanup first
rm onewire.out
rm onewire.vcd
 
# list of source files
sources="../hdl/onewire_tb.v ../hdl/onewire_slave_model.v ../hdl/sockit_owm.v"
 
# compile verilog sources (testbench and RTL) and run simulation
 
# data bus widths
for buswdth in "BDW_32" "BDW_8"
do
  # clock divider implementation
  for divider in "CDR_NONE" "CDR_E"
  do
    # timing options
    for preset in "PRESET_50_10" "PRESET_60_05" "PRESET_75"
    do
      iverilog -o onewire.out $sources -D$preset -D$divider -D$buswdth
      vvp onewire.out -none
    done
  done
done
 
# test a single 1-wire line configuration (waveform generation is enabled)
iverilog -o onewire.out $sources -DPRESET_50_10 -DCDR_NONE -DBDW_32 -DOWN=1
vvp onewire.out
 
# open the waveform and detach it
gtkwave onewire.vcd gtkwave.sav &