Subversion Repositories trigonometric_functions_in_double_fpu

/////////////////////////////////////////////////////////////////////
////                                                             ////
////                                                          ////
////  Trigonometric functions using double precision Floating Point Unit        ////
////                                                             ////
////  Author: Muni Aditya                                        ////
////          muni_aditya@yahoo.com                                ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2013 Muni Aditya                           ////
////                  muni_aditya@yahoo.com                        ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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/////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 100ps
 
`define INPUT_WIDTH 32
 
 
 
module dividor (clk, inp, rst, out);
 
  input clk;
  input [`INPUT_WIDTH-1:0] inp;
  input rst;
 
//////////////inputs/////////////////
 
  output  reg [`INPUT_WIDTH-1:0] out;
 
//////////////output/////////////////  
 
 wire [`INPUT_WIDTH-1:0]DIVISOR = `INPUT_WIDTH'd360 ;
 
 
  always @ (posedge clk)
 
// modulo division 
 
   if(rst)
     out <= 8'd0 ;
   else 
    out <= inp % DIVISOR ;
 
 
 
 
 
 endmodule