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URL https://opencores.org/ocsvn/uart2spi/uart2spi/trunk

Subversion Repositories uart2spi

[/] [uart2spi/] [trunk/] [verif/] [run/] [run_modelsim] - Rev 3

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#!/bin/csh -f
#
# test for uart
#

echo " Compiling with MODELSIM "

if(! -e work) then
   vlib work
endif
vlog -work work  +define+SFLASH_SPDUP \
+incdir+../models/st_m25p16 \
+incdir+../tb  \
./time_scale.v \
../../rtl/top/top.v \
../../rtl/uart_core/uart_core.v \
../../rtl/uart_core/clk_ctl.v \
../../rtl/uart_core/uart_rxfsm.v \
../../rtl/uart_core/uart_txfsm.v \
../../rtl/msg_hand/uart_msg_handler.v \
../../rtl/spi/spi_core.v  \
../../rtl/spi/spi_ctl.v  \
../../rtl/spi/spi_if.v \
../../rtl/spi/spi_cfg.v \
../../rtl/lib/registers.v \
../tb/tb_top.v  \
../models/st_m25p16/acdc_check.v  \
../models/st_m25p16/internal_logic.v  \
../models/st_m25p16/memory_access.v  \
../models/st_m25p16/M25p16.v \
../tb/uart_agent.v  \
-l ../log/compile_modelsim.log

vsim -do modelsim.do -c tb_top | tee  ../log/run_modelsim.log

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