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https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [coregen.cgp] - Rev 2
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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = ftg256
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false