URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Subversion Repositories usb_fpga_2_14
[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [sim/] [mem0.prj] - Rev 2
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verilog work ../rtl/infrastructure.v
verilog work ../rtl/mem0.v
verilog work ../rtl/memc_wrapper.v
verilog work ../rtl/mcb_controller/iodrp_controller.v
verilog work ../rtl/mcb_controller/iodrp_mcb_controller.v
verilog work ../rtl/mcb_controller/mcb_raw_wrapper.v
verilog work ../rtl/mcb_controller/mcb_soft_calibration.v
verilog work ../rtl/mcb_controller/mcb_soft_calibration_top.v
verilog work ../rtl/mcb_controller/mcb_ui_top.v
verilog work ./afifo.v
verilog work ./cmd_gen.v
verilog work ./cmd_prbs_gen.v
verilog work ./data_prbs_gen.v
verilog work ./init_mem_pattern_ctr.v
verilog work ./mcb_flow_control.v
verilog work ./mcb_traffic_gen.v
verilog work ./rd_data_gen.v
verilog work ./read_data_path.v
verilog work ./read_posted_fifo.v
verilog work ./sp6_data_gen.v
verilog work ./tg_status.v
verilog work ./v6_data_gen.v
verilog work ./wr_data_gen.v
verilog work ./write_data_path.v
verilog work ./memc_tb_top.v
verilog work $XILINX/verilog/src/glbl.v
verilog work ./sim_tb_top.v
verilog work ./ddr_model_c3.v -d x512Mb -d FULL_MEM -d sg5B -d x16 -i ./