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[/] [versatile_io/] [trunk/] [rtl/] [verilog/] [include/] [versatile_io_defines.v] - Rev 2
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//=tab Main //=comment <b>Versatile IO</b> //=tab UART `define UART0 `define UART0_BASE 32'h92000000 `define UART0_MEM_MAP_HI 31 `define UART0_MEM_MAP_LO 24 //=comment //`define UART1 `define UART1_BASE 32'h92100000 `define UART1_MEM_MAP_HI 31 `define UART1_MEM_MAP_LO 24
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