Subversion Repositories wbddr3

////////////////////////////////////////////////////////////////////////////////
//
// Filename: 	wbddrsdram.v
//
// Project:	OpenArty, an entirely open SoC based upon the Arty platform
//
// Purpose:	
//
// Creator:	Dan Gisselquist, Ph.D.
//		Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of  the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program.  (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.)  If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License:	GPL, v3, as defined and found on www.gnu.org,
//		http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
 
// Possible commands to the DDR3 memory.  These consist of settings for the
// bits: o_wb_cs_n, o_wb_ras_n, o_wb_cas_n, and o_wb_we_n, respectively.
`define	DDR_MRSET	4'b0000
`define	DDR_REFRESH	4'b0001
`define	DDR_PRECHARGE	4'b0010
`define	DDR_ACTIVATE	4'b0011
`define	DDR_WRITE	4'b0100
`define	DDR_READ	4'b0101
`define	DDR_NOOP	4'b0111
//`define	DDR_DESELECT	4'b1???
//
// In this controller, 24-bit commands tend to be passed around.  These 
// 'commands' are bit fields.  Here we specify the bits associated with
// the bit fields.
`define	DDR_RSTDONE	26	// End the reset sequence?
`define	DDR_RSTTIMER	25	// Does this reset command take multiple clocks?
`define	DDR_RSTBIT	24	// Value to place on reset_n
`define	DDR_CKEBIT	23	// Should this reset command set CKE?
`define	DDR_CMDLEN	23
`define	DDR_CSBIT	22
`define	DDR_RASBIT	21
`define	DDR_CASBIT	20
`define	DDR_WEBIT	19
`define	DDR_NOPTIMER	18	// Steal this from BA bits
`define	DDR_BABITS	3	// BABITS are really from 18:16, they are 3 bits
`define	DDR_ADDR_BITS	14
 
module	wbddrsdram(i_clk, i_reset,
		i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
			o_wb_ack, o_wb_stall, o_wb_data,
		o_ddr_reset_n, o_ddr_cke,
		o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n, o_ddr_we_n,
		o_ddr_dqs, o_ddr_dm, o_ddr_odt, o_ddr_bus_dir,
		o_ddr_addr, o_ddr_ba, o_ddr_data, i_ddr_data);
	parameter	CKREFI4 = 13'd6240, // 4 * 7.8us at 200 MHz clock
			CKRFC = 140;
	input			i_clk, i_reset;
	// Wishbone inputs
	input			i_wb_cyc, i_wb_stb, i_wb_we;
	input		[25:0]	i_wb_addr;
	input		[31:0]	i_wb_data;
	// Wishbone outputs
	output	reg		o_wb_ack;
	output	reg		o_wb_stall;
	output	reg	[31:0]	o_wb_data;
	// DDR3 RAM Controller
	output	wire		o_ddr_reset_n, o_ddr_cke;
	// Control outputs
	output	reg		o_ddr_cs_n, o_ddr_ras_n, o_ddr_cas_n,o_ddr_we_n;
	// DQS outputs:set to 3'b010 when data is active, 3'b100 (i.e. 2'bzz) ow
	output	wire		o_ddr_dqs;
	output	reg		o_ddr_dm, o_ddr_odt, o_ddr_bus_dir;
	// Address outputs
	output	reg	[13:0]	o_ddr_addr;
	output	reg	[2:0]	o_ddr_ba;
	// And the data inputs and outputs
	output	reg	[31:0]	o_ddr_data;
	input			i_ddr_data;
 
	reg		drive_dqs;
 
	// The pending transaction
	reg	[31:0]	r_data;
	reg		r_pending, r_we;
	reg	[25:0]	r_addr;
	reg	[14:0]	r_row;
	reg	[2:0]	r_bank;
	reg	[9:0]	r_col;
	reg	[1:0]	r_sub;
	reg		r_move; // It was accepted, and can move to next stage
 
	// Can the pending transaction be satisfied with the current (ongoing)
	// transaction?
	reg		m_move, m_match, m_continue, m_pending, m_we;
	reg	[25:0]	m_addr;
	reg	[14:0]	m_row;
	reg	[2:0]	m_bank;
	reg	[9:0]	m_col;
	reg	[1:0]	m_sub;
 
	// Can we preload the next bank?
	reg	[14:0]	r_nxt_row;
	reg	[2:0]	r_nxt_bank;
 
//
// tWTR = 7.5
// tRRD = 7.5
// tREFI= 7.8
// tFAW = 45
// tRTP = 7.5
// tCKE = 5.625
// tRFC = 160
// tRP  = 13.5
// tRAS = 36
// tRCD = 13.5
//
// RESET:
//	1. Hold o_reset_n = 1'b0; for 200 us, or 40,000 clocks (65536 perhaps?)
//		Hold cke low during this time as well
//		The clock should be free running into the chip during this time
//		Leave command in NOOP state: {cs,ras,cas,we} = 4'h7;
//		ODT must be held low
//	2. Hold cke low for another 500us, or 100,000 clocks
//	3. Raise CKE, continue outputting a NOOP for
//		tXPR, tDLLk, and tZQInit
//	4. Load MRS2, wait tMRD
//	4. Load MRS3, wait tMRD
//	4. Load MRS1, wait tMOD
// Before using the SDRAM, we'll need to program at least 3 of the mode
//	registers, if not all 4. 
//   tMOD clocks are required to program the mode registers, during which
//	time the RAM must be idle.
//
// NOOP: CS low, RAS, CAS, and WE high
 
//
// Reset logic should be simple, and is given as follows:
// note that it depends upon a ROM memory, reset_mem, and an address into that
// memory: reset_address.  Each memory location provides either a "command" to
// the DDR3 SDRAM, or a timer to wait until the next command.  Further, the
// timer commands indicate whether or not the command during the timer is to
// be set to idle, or whether the command is instead left as it was.
	reg		reset_override, reset_ztimer;
	reg	[3:0]	reset_address;
	reg	[(`DDR_CMDLEN-1):0]	reset_cmd, cmd, refresh_cmd;
	reg	[26:0]	reset_instruction;
	reg	[16:0]	reset_timer;
	initial	reset_override = 1'b1;
	initial	reset_address  = 4'h0;
	always @(posedge i_clk)
		if (i_reset)
		begin
			reset_override <= 1'b1;
			reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
		end else if (!reset_ztimer)
			;
		else if (reset_instruction[`DDR_RSTDONE])
			reset_override <= 1'b0;
		else if (reset_instruction[`DDR_RSTTIMER])
		begin
			if (reset_instruction[`DDR_NOPTIMER])
				reset_cmd <= { `DDR_NOOP, reset_instruction[18:0]};
		end else begin
			reset_cmd <= reset_instruction[22:0];
		end
	always @(posedge i_clk)
		if (i_reset)
			o_ddr_cke <= 1'b0;
		else if ((reset_override)&&(reset_ztimer))
			o_ddr_cke <= reset_instruction[`DDR_CKEBIT];
 
	initial	reset_ztimer = 1'b1;	// Is the timer zero?
	initial	reset_timer = 17'h00;
	always @(posedge i_clk)
		if (i_reset)
		begin
			reset_ztimer <= 1'b0;
			reset_timer <= 17'h00;
		end else if (!reset_ztimer)
		begin
			reset_ztimer <= (reset_timer == 17'h01);
			reset_timer <= reset_timer - 17'h01;
		end else if (reset_instruction[`DDR_RSTTIMER])
		begin
			reset_ztimer <= 1'b0;
			reset_timer <= reset_instruction[16:0];
		end
 
 
	always @(posedge i_clk)
		case(reset_address) // RSTDONE, TIMER, CKE, ??
		4'h0: reset_instruction <= { 4'h4, `DDR_NOOP, 19'd40_000 };
		4'h1: reset_instruction <= { 4'h6, `DDR_NOOP, 19'd100_000 };
		4'h2: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
		4'h3: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h0, 3'h0, 1'b0, 3'h1, 1'b0, 1'b0, 3'h1, 1'b0, 1'b0, 2'b00 }; // MRS
		4'h4: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
		4'h5: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h2, 5'h0, 2'b00, 1'b0, 1'b0, 1'b1, 3'b0, 3'b0 }; // MRS2
		4'h6: reset_instruction <= { 4'h7, `DDR_NOOP, 19'd40_000 };
		4'h7: reset_instruction <= { 4'h3, `DDR_MRSET, 3'h1, 3'h0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 2'b0, 1'b1, 1'b0, 2'b0, 1'b1, 1'b1, 1'b0 }; // MRS1
		default:
			reset_instruction <={4'hb, `DDR_NOOP, 19'd00_000 };
		endcase
		// reset_instruction <= reset_mem[reset_address];
 
	always @(posedge i_clk)
		if (i_reset)
			reset_address <= 4'h0;
		else if (reset_ztimer)
			reset_address <= reset_address + 4'h1;
//
// initial reset_mem =
//	 0.	!DONE, TIMER,RESET_N=0, CKE=0, CMD = NOOP, TIMER = 200us ( 40,000)
//	 1.	!DONE, TIMER,RESET_N=1, CKE=0, CMD = NOOP, TIMER = 500us (100,000)
//	 2.	!DONE, TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = (Look me up)
//	 3.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS
//	 4.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
//	 5.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS3
//	 6.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
//	 7.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
//	 8.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMRS
//	 9.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = MODE, MRS1
//	10.	!DONE,!TIMER,RESET_N=1, CKE=1, CMD = NOOP, TIMER = tMOD
//	11.	!DONE,!TIMER,RESET_N=1, CKE=1, (Pre-charge all)
//	12.	!DONE,!TIMER,RESET_N=1, CKE=1, (wait)
//	13.	!DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
//	14.	!DONE,!TIMER,RESET_N=1, CKE=1, (Auto-refresh)
//	15.	!DONE,!TIMER,RESET_N=1, CKE=1, (wait)
 
 
//
//
// Let's keep track of any open banks.  There are 8 of them to keep track of.
//
//	A precharge requires 3 clocks at 200MHz to complete, 2 clocks at 100MHz.
//	
//
//
	reg	need_refresh;
 
	wire	w_precharge_all;
	reg	banks_are_closing, all_banks_closed;
	reg	[2:0]	bank_status[7:0];
	always @(posedge i_clk)
	begin
		bank_status[0] = { bank_status[0][1:0], bank_status[0][0] };
		bank_status[1] = { bank_status[1][1:0], bank_status[1][0] };
		bank_status[2] = { bank_status[2][1:0], bank_status[2][0] };
		bank_status[3] = { bank_status[3][1:0], bank_status[3][0] };
		bank_status[4] = { bank_status[4][1:0], bank_status[4][0] };
		bank_status[5] = { bank_status[5][1:0], bank_status[5][0] };
		bank_status[6] = { bank_status[6][1:0], bank_status[6][0] };
		bank_status[7] = { bank_status[7][1:0], bank_status[7][0] };
		all_banks_closed <= (bank_status[0][1:0] == 2'b00)
					&&(bank_status[1][1:0] == 2'b00)
					&&(bank_status[2][1:0] == 2'b00)
					&&(bank_status[3][1:0] == 2'b00)
					&&(bank_status[4][1:0] == 2'b00)
					&&(bank_status[5][1:0] == 2'b00)
					&&(bank_status[6][1:0] == 2'b00)
					&&(bank_status[7][1:0] == 2'b00);
		if ((!reset_override)&&(need_refresh)||(w_precharge_all))
		begin
			bank_status[0][0] = 1'b0;
			bank_status[1][0] = 1'b0;
			bank_status[2][0] = 1'b0;
			bank_status[3][0] = 1'b0;
			bank_status[4][0] = 1'b0;
			bank_status[5][0] = 1'b0;
			bank_status[6][0] = 1'b0;
			bank_status[7][0] = 1'b0;
			banks_are_closing <= 1'b1;
		end else if (need_close_bank)
		begin
			bank_status[r_bank][0] = 1'b0;
		end else if (need_open_bank)
		begin
			bank_status[r_bank][0] = 1'b1;
			all_banks_closed <= 1'b0;
			banks_are_closing <= 1'b0;
		end
	end
 
	always @(posedge i_clk)
		// if (cmd[22:19] == `DDR_ACTIVATE)
		if (need_open_bank)
			bank_address[activate_bank_cmd[18:16]]
				<= activate_bank_cmd[14:0];
 
//
//
// Okay, let's investigate when we need to do a refresh.  Our plan will be to
// do 4 refreshes every tREFI*4 seconds.  tREFI = 7.8us, but its a parameter
// in the number of clocks so that we can handle both 100MHz and 200MHz clocks.
//
// Note that 160ns are needed between refresh commands (JEDEC, p172), or
// 320 clocks @200MHz, or equivalently 160 clocks @100MHz.  Thus to issue 4
// of these refresh cycles will require 4*320=1280 clocks@200 MHz.  After this
// time, no more refreshes will be needed for 6240 clocks.
//
// Let's think this through:
//	REFRESH_COST = (n*(320)+24)/(n*1560)
// 
//
//
	reg		midrefresh, refresh_clear, endrefresh;
	reg	[12:0]	refresh_clk;
	reg	[2:0]	midrefresh_hctr; // How many refresh cycles?
	reg	[8:0]	midrefresh_lctr; // How many clks in this refresh cycle
	always @(posedge i_clk)
		if ((reset_override)||(refresh_clear))
			refresh_clk <= CKREFI4;
		else if (|refresh_clk)
			refresh_clk <= refresh_clk-1;
	always @(posedge i_clk)
		need_refresh <= (refresh_clk == 0)||(midrefresh);
	always @(posedge i_clk)
		if (!need_refresh)
			refresh_cmd <= { `DDR_NOOP, 19'h00 };
		else if (~banks_are_closing)
			refresh_cmd <= { `DDR_PRECHARGE, 3'h0, 5'h0, 1'b1, 10'h00 };
		else if (~all_banks_closed)
			refresh_cmd <= { `DDR_NOOP, 19'h00 };
		else
			refresh_cmd <= { `DDR_REFRESH, 19'h00 };
	always @(posedge i_clk)
		midrefresh <= (need_refresh)&&(all_banks_closed)&&(~refresh_clear);
 
	always @(posedge i_clk)
		if (!midrefresh)
			midrefresh_hctr <= 3'h4;
		else if ((midrefresh_lctr == 0)&&(|midrefresh_hctr))
			midrefresh_hctr <= midrefresh_hctr - 1;
	always @(posedge i_clk)
		if ((!need_refresh)||(!midrefresh))
			endrefresh <= 1'b0;
		else if (midrefresh_hctr == 3'h0)
			endrefresh <= 1'b1;
	always @(posedge i_clk)
		if (!midrefresh)
			midrefresh_lctr <= CKRFC;
		else if (midrefresh_lctr == 0)
			midrefresh_lctr <= 0;
		else
			midrefresh_lctr <= CKRFC;
 
	always @(posedge i_clk)
		refresh_clear <= (need_refresh)&&(endrefresh)&&(midrefresh_lctr == 0);
 
 
//
//
//	Let's track: when will our bus be active?  When will we be reading or
//	writing?
//
//
	reg	[8:0]	bus_active, bus_read;
	reg	[1:0]	bus_subaddr	[8:0];
	initial	bus_active = 0;
	always @(posedge i_clk)
	begin
		bus_active[8:0] <= { bus_active[7:0], 1'b0 };
		bus_read[8:0]   <= { bus_read[7:0], 1'b0 }; // Drive the d-bus?
		//bus_mask[8:0] <= { bus_mask[7:0], 1'b1 }; // Write this value?
		bus_subaddr[8]  <= bus_subaddr[7];
		bus_subaddr[7]  <= bus_subaddr[6];
		bus_subaddr[6]  <= bus_subaddr[5];
		bus_subaddr[5]  <= bus_subaddr[4];
		bus_subaddr[4]  <= bus_subaddr[3];
		bus_subaddr[3]  <= bus_subaddr[2];
		bus_subaddr[2]  <= bus_subaddr[1];
		bus_subaddr[1]  <= bus_subaddr[0];
		bus_subaddr[0]  <= 2'h3;
		if (cmd[22:19] == `DDR_READ)
		begin
			bus_active[3:0]<= 4'hf; // Once per clock
			bus_read[3:0]  <= 4'hf; // These will be reads
			bus_subaddr[3] <= 2'h0;
			bus_subaddr[2] <= 2'h1;
			bus_subaddr[1] <= 2'h2;
		end else if (cmd == `DDR_WRITE)
		begin
			bus_active[3:0] <= 4'hf;
			// bus_read[7:4] = 4'h0;
			bus_subaddr[3] <= 2'h0;
			bus_subaddr[2] <= 2'h1;
			bus_subaddr[1] <= 2'h2;
		end
	end
 
	always @(posedge i_clk)
		drive_dqs <= (~bus_read[8])&&(|bus_active[8:7]);
 
//
//
// Now, let's see, can we issue a read command?
//
//
	always @(posedge i_clk)
	begin
		if ((i_wb_stb)&&(~o_wb_stall))
		begin
			r_pending <= 1'b1;
			o_wb_stall <= 1'b1;
		end else if ((r_move)||(m_move))
		begin
			r_pending <= 1'b0;
			o_wb_stall <= 1'b0;
		end
 
		if (~o_wb_stall)
		begin
			r_we   <= i_wb_we;
			r_addr <= i_wb_addr;
			r_data <= i_wb_data;
			r_row  <= i_wb_addr[25:11];
			r_bank <= i_wb_addr[10:8];
			r_col  <= { i_wb_addr[7:2], 2'b00 }; // 9:2
			r_sub  <= i_wb_addr[1:0];
 
			// pre-emptive work
			r_nxt_row  <= i_wb_addr[25:11]+15'h1;
			r_nxt_bank <= i_wb_addr[10:8]+3'h1;
		end
	end
 
	reg	[2:0]	bank_active[7:0];
	reg	[14:0]	bank_address[7:0];
 
	reg	[(`DDR_CMDLEN-1):0]	close_bank_cmd, activate_bank_cmd, rw_cmd;
	reg	need_close_bank, need_close_this_bank,
			last_close_bank, maybe_close_next_bank,
		need_open_bank, last_open_bank, maybe_open_next_bank,
		valid_bank, last_valid_bank;
	always @(posedge i_clk)
	begin
		need_close_bank <= (r_pending)&&(bank_active[r_bank][0])
			&&(r_row != bank_address[r_bank])&&(!last_close_bank);
		need_close_this_bank <= (r_pending)&&(bank_active[r_bank][0])
			&&(r_row != bank_address[r_bank]);
		last_close_bank <= need_close_bank;
 
		maybe_close_next_bank <= (r_pending)
			&&(bank_active[r_nxt_bank][0])
			&&(r_nxt_row != bank_address[r_nxt_bank])
			&&(!need_close_this_bank);
 
		close_bank_cmd <= (maybe_close_next_bank)
				? { `DDR_PRECHARGE, r_nxt_bank, r_nxt_row[14:10], 1'b0, r_nxt_row[9:0] }
				: { `DDR_PRECHARGE, r_bank, r_row[15:11], 1'b0, r_row[9:0] };
 
 
		need_open_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b00)
			&&(!last_open_bank);
		last_open_bank <= need_open_bank;
 
		maybe_open_next_bank <= (r_pending)
			&&(bank_active[r_nxt_bank][1:0] == 2'b00)
			&&(!need_open_bank)&&(!need_close_bank);
 
		activate_bank_cmd <= (maybe_open_next_bank)
				? { `DDR_ACTIVATE,r_nxt_bank,1'b0,r_nxt_row[14:0] }
				: { `DDR_ACTIVATE, r_bank, 1'b0,r_row[14:0] };
 
 
 
		valid_bank <= (r_pending)&&(bank_active[r_bank][1:0]==2'b11)
				&&(bank_address[r_bank]==r_row)
				&&(!last_valid_bank);
		last_valid_bank <= valid_bank;
 
		rw_cmd[`DDR_CSBIT:`DDR_WEBIT] <= (~r_pending)?`DDR_NOOP:((r_we)?`DDR_WRITE:`DDR_READ);
		rw_cmd[`DDR_WEBIT-1:0] <= { r_bank, 5'h0, 1'b0, r_col };
	end
 
 
	// Match registers, to see if we can move forward without sending a
	// new command
	always @(posedge i_clk)
	begin
		if (r_move)
		begin
			m_pending <= r_pending;
			m_we   <= r_we;
			m_addr <= r_addr;
			m_row  <= r_row;
			m_bank <= r_bank;
			m_col  <= r_col;
			m_sub  <= r_sub;
		end else if (m_match)
			m_sub <= r_sub;
 
		m_match <= (m_pending)&&(r_pending)&&(r_we == m_we)
				&&(r_row == m_row)&&(r_bank == m_bank)
				&&(r_col == m_col)
				&&(r_sub > m_sub);
		m_continue <= (m_pending)&&(r_pending)&&(r_we == m_we)
				&&(r_row == m_row)&&(r_bank == m_bank)
				&&(r_col == m_col+10'h1);
		// m_nextbank <= (m_pending)&&(r_pending)&&(r_we == m_we)
		//		&&(r_row == m_row)&&(r_bank == m_bank);
	end
 
//
//
// Okay, let's look at the last assignment in our chain.  It should look
// something like:
	always @(posedge i_clk)
		o_ddr_reset_n <= (~reset_override)||(reset_instruction[`DDR_RSTBIT]);
	always @(posedge i_clk)
		o_ddr_cke <= (~reset_override)||(reset_instruction[`DDR_CKEBIT]);
	always @(posedge i_clk)
	begin
		r_move <= 1'b0;
		if (reset_override)
			cmd <= reset_cmd[`DDR_CSBIT:0];
		else if (need_refresh)
		begin
			cmd <= refresh_cmd; // The command from the refresh logc
		end else if (need_close_bank)
			cmd <= close_bank_cmd;
		else if (need_open_bank)
			cmd <= activate_bank_cmd;
		else if ((valid_bank)&&(bus_active[2:0]==3'h0))
		begin
			cmd <= rw_cmd;
			r_move <= 1'b1;
		end else
			cmd <= { `DDR_NOOP, rw_cmd[20:0] };
	end
 
	reg	[31:0]	bus_data[8:0];
 
	assign	o_ddr_cs_n  = cmd[`DDR_CSBIT];
	assign	o_ddr_ras_n = cmd[`DDR_RASBIT];
	assign	o_ddr_cas_n = cmd[`DDR_CASBIT];
	assign	o_ddr_we_n  = cmd[`DDR_WEBIT];
	assign	o_ddr_dqs   = drive_dqs;
	assign	o_ddr_addr  = cmd[(`DDR_ADDR_BITS-1):0];
	assign	o_ddr_ba    = cmd[(`DDR_BABITS+`DDR_ADDR_BITS-1):`DDR_ADDR_BITS];
	assign	o_ddr_data  = bus_data[8];
	assign	w_precharge_all = (cmd[`DDR_CSBIT:`DDR_WEBIT]==`DDR_PRECHARGE)
				&&(o_ddr_addr[10]); // 5 bits
 
	// Need to set o_wb_dqs high one clock prior to any read.
	// As per spec, ODT = 0 during reads
	assign	o_ddr_bus_dir = bus_read[8];
	assign	o_ddr_odt = o_ddr_bus_dir;
 
 
endmodule