Subversion Repositories wiegand_ctl

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.12 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.14 secs
 
--> Reading design: wiegand_tx_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
        9.1) Device utilization summary
        9.2) Partition Resource Summary
        9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "wiegand_tx_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "wiegand_tx_top"
Output Format                      : NGC
Target Device                      : xc3s700an-4-fgg484

---- Source Options
Top Module Name                    : wiegand_tx_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../../../../rtl/verilog/wb_interface.v" in library work
Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
Compiling verilog file "../../../../../rtl/verilog/fifos.v" in library work
Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
Module <wb_interface_wieg> compiled
Module <fifo_wieg> compiled
Module <custom_fifo_dp> compiled
Compiling verilog file "../../../../../rtl/verilog/wiegand_tx_top.v" in library work
Compiling verilog include file "../../../../../rtl/verilog/wiegand_defines.v"
Module <mem_byte> compiled
Module <wiegand_tx_top> compiled
No errors in compilation
Analysis of file <"wiegand_tx_top.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <wiegand_tx_top> in library <work>.

Analyzing hierarchy for module <fifo_wieg> in library <work>.

Analyzing hierarchy for module <wb_interface_wieg> in library <work>.

Analyzing hierarchy for module <custom_fifo_dp> in library <work>.

Analyzing hierarchy for module <mem_byte> in library <work>.


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <wiegand_tx_top>.
Module <wiegand_tx_top> is correct for synthesis.
 
Analyzing module <fifo_wieg> in library <work>.
Module <fifo_wieg> is correct for synthesis.
 
Analyzing module <custom_fifo_dp> in library <work>.
Module <custom_fifo_dp> is correct for synthesis.
 
Analyzing module <mem_byte> in library <work>.
Module <mem_byte> is correct for synthesis.
 
Analyzing module <wb_interface_wieg> in library <work>.
Module <wb_interface_wieg> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <wb_interface_wieg>.
    Related source file is "../../../../../rtl/verilog/wb_interface.v".
WARNING:Xst:647 - Input <dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_cti_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_sel_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <p2p>.
    Found 32-bit tristate buffer for signal <wb_dat_o>.
    Found 32-bit register for signal <pulsewidth>.
    Found 1-bit register for signal <ack>.
    Found 1-bit register for signal <err>.
    Found 1-bit register for signal <rty>.
    Found 9-bit register for signal <size>.
    Found 32-bit 4-to-1 multiplexer for signal <wb_dat_rdbk>.
    Summary:
        inferred  44 D-type flip-flop(s).
        inferred  32 Multiplexer(s).
        inferred  32 Tristate(s).
Unit <wb_interface_wieg> synthesized.


Synthesizing Unit <mem_byte>.
    Related source file is "../../../../../rtl/verilog/fifos.v".
    Found 8-bit tristate buffer for signal <dout>.
    Found 8-bit register for signal <byte_reg>.
    Summary:
        inferred   8 D-type flip-flop(s).
        inferred   8 Tristate(s).
Unit <mem_byte> synthesized.


Synthesizing Unit <custom_fifo_dp>.
    Related source file is "../../../../../rtl/verilog/fifos.v".
    Found 3-bit comparator equal for signal <empty>.
    Found 3-bit register for signal <addr_rd>.
    Found 3-bit register for signal <addr_wr>.
    Found 8-bit register for signal <fifo_out>.
    Summary:
        inferred  14 D-type flip-flop(s).
        inferred   1 Comparator(s).
Unit <custom_fifo_dp> synthesized.


Synthesizing Unit <fifo_wieg>.
    Related source file is "../../../../../rtl/verilog/fifos.v".
Unit <fifo_wieg> synthesized.


Synthesizing Unit <wiegand_tx_top>.
    Related source file is "../../../../../rtl/verilog/wiegand_tx_top.v".
WARNING:Xst:646 - Signal <empty> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 12                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk                       (rising_edge)        |
    | Reset              | rst                       (positive)           |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <one_o>.
    Found 1-bit register for signal <zero_o>.
    Found 7-bit up counter for signal <bitCount>.
    Found 7-bit up counter for signal <bitCountReg>.
    Found 1-bit register for signal <full_dly>.
    Found 1-bit register for signal <lock_cfg>.
    Found 5-bit up counter for signal <p2pCnt>.
    Found 32-bit up counter for signal <pulseCnt>.
    Found 32-bit comparator equal for signal <state$cmp_eq0001> created at line 192.
    Found 7-bit comparator equal for signal <state$cmp_eq0002> created at line 193.
    Found 32-bit comparator equal for signal <state$cmp_eq0003> created at line 202.
    Found 32-bit register for signal <word_out>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   4 Counter(s).
        inferred  36 D-type flip-flop(s).
        inferred   3 Comparator(s).
Unit <wiegand_tx_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 4
 32-bit up counter                                     : 1
 5-bit up counter                                      : 1
 7-bit up counter                                      : 2
# Registers                                            : 51
 1-bit register                                        : 31
 32-bit register                                       : 3
 8-bit register                                        : 16
 9-bit register                                        : 1
# Comparators                                          : 7
 3-bit comparator equal                                : 4
 32-bit comparator equal                               : 2
 7-bit comparator equal                                : 1
# Multiplexers                                         : 1
 32-bit 4-to-1 multiplexer                             : 1
# Tristates                                            : 13
 32-bit tristate buffer                                : 1
 8-bit tristate buffer                                 : 12

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <state/FSM> on signal <state[1:3]> with gray encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 100   | 010
 101   | 011
 110   | 111
 111   | 110
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# Counters                                             : 4
 32-bit up counter                                     : 1
 5-bit up counter                                      : 1
 7-bit up counter                                      : 2
# Registers                                            : 264
 Flip-Flops                                            : 264
# Comparators                                          : 7
 3-bit comparator equal                                : 4
 32-bit comparator equal                               : 2
 7-bit comparator equal                                : 1
# Multiplexers                                         : 1
 32-bit 4-to-1 multiplexer                             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2042 - Unit mem_byte: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.

Optimizing unit <wiegand_tx_top> ...

Optimizing unit <custom_fifo_dp> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block wiegand_tx_top, actual ratio is 3.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 318
 Flip-Flops                                            : 318

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : wiegand_tx_top.ngr
Top Level Output File Name         : wiegand_tx_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 87

Cell Usage :
# BELS                             : 414
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 7
#      LUT2_D                      : 2
#      LUT2_L                      : 1
#      LUT3                        : 39
#      LUT3_D                      : 3
#      LUT3_L                      : 1
#      LUT4                        : 245
#      LUT4_L                      : 6
#      MUXCY                       : 63
#      MUXF5                       : 12
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 318
#      FDC                         : 76
#      FDC_1                       : 3
#      FDCE                        : 158
#      FDCE_1                      : 69
#      FDPE                        : 8
#      FDPE_1                      : 4
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 79
#      IBUF                        : 42
#      OBUF                        : 5
#      OBUFT                       : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s700anfgg484-4 

 Number of Slices:                      243  out of   5888     4%  
 Number of Slice Flip Flops:            318  out of  11776     2%  
 Number of 4 input LUTs:                305  out of  11776     2%  
 Number of IOs:                          87
 Number of bonded IOBs:                  80  out of    372    21%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
wb_clk_i                           | BUFGP                  | 318   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+----------------------------------------------+-------+
Control Signal                     | Buffer(FF name)                              | Load  |
-----------------------------------+----------------------------------------------+-------+
wb_rst_i                           | IBUF                                         | 166   |
_or0000(_or00001:O)                | NONE(datafifowrite/custom_fifo_dp5/addr_rd_0)| 152   |
-----------------------------------+----------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 12.521ns (Maximum Frequency: 79.865MHz)
   Minimum input arrival time before clock: 7.398ns
   Maximum output required time after clock: 7.061ns
   Maximum combinational path delay: 9.636ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'wb_clk_i'
  Clock period: 12.521ns (frequency: 79.865MHz)
  Total number of paths / destination ports: 3668 / 390
-------------------------------------------------------------------------
Delay:               6.261ns (Levels of Logic = 33)
  Source:            state_FSM_FFd1 (FF)
  Destination:       pulseCnt_31 (FF)
  Source Clock:      wb_clk_i rising
  Destination Clock: wb_clk_i falling

  Data Path: state_FSM_FFd1 to pulseCnt_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             52   0.591   1.349  state_FSM_FFd1 (state_FSM_FFd1)
     LUT4:I1->O            1   0.643   0.000  Mcount_pulseCnt_lut<0> (Mcount_pulseCnt_lut<0>)
     MUXCY:S->O            1   0.632   0.000  Mcount_pulseCnt_cy<0> (Mcount_pulseCnt_cy<0>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<1> (Mcount_pulseCnt_cy<1>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<2> (Mcount_pulseCnt_cy<2>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<3> (Mcount_pulseCnt_cy<3>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<4> (Mcount_pulseCnt_cy<4>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<5> (Mcount_pulseCnt_cy<5>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<6> (Mcount_pulseCnt_cy<6>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<7> (Mcount_pulseCnt_cy<7>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<8> (Mcount_pulseCnt_cy<8>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<9> (Mcount_pulseCnt_cy<9>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<10> (Mcount_pulseCnt_cy<10>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<11> (Mcount_pulseCnt_cy<11>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<12> (Mcount_pulseCnt_cy<12>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<13> (Mcount_pulseCnt_cy<13>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<14> (Mcount_pulseCnt_cy<14>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<15> (Mcount_pulseCnt_cy<15>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<16> (Mcount_pulseCnt_cy<16>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<17> (Mcount_pulseCnt_cy<17>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<18> (Mcount_pulseCnt_cy<18>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<19> (Mcount_pulseCnt_cy<19>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<20> (Mcount_pulseCnt_cy<20>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<21> (Mcount_pulseCnt_cy<21>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<22> (Mcount_pulseCnt_cy<22>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<23> (Mcount_pulseCnt_cy<23>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<24> (Mcount_pulseCnt_cy<24>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<25> (Mcount_pulseCnt_cy<25>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<26> (Mcount_pulseCnt_cy<26>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<27> (Mcount_pulseCnt_cy<27>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<28> (Mcount_pulseCnt_cy<28>)
     MUXCY:CI->O           1   0.065   0.000  Mcount_pulseCnt_cy<29> (Mcount_pulseCnt_cy<29>)
     MUXCY:CI->O           0   0.065   0.000  Mcount_pulseCnt_cy<30> (Mcount_pulseCnt_cy<30>)
     XORCY:CI->O           1   0.844   0.000  Mcount_pulseCnt_xor<31> (Mcount_pulseCnt31)
     FDC:D                     0.252          pulseCnt_31
    ----------------------------------------
    Total                      6.261ns (4.912ns logic, 1.349ns route)
                                       (78.5% logic, 21.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'wb_clk_i'
  Total number of paths / destination ports: 959 / 255
-------------------------------------------------------------------------
Offset:              7.398ns (Levels of Logic = 5)
  Source:            wb_adr_i<4> (PAD)
  Destination:       wb_interface/pulsewidth_0 (FF)
  Destination Clock: wb_clk_i falling

  Data Path: wb_adr_i<4> to wb_interface/pulsewidth_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.849   0.590  wb_adr_i_4_IBUF (wb_adr_i_4_IBUF)
     LUT3:I0->O            1   0.648   0.500  _and000011_SW0 (N115)
     LUT4:I1->O            4   0.643   0.590  _and000011 (N34)
     LUT4:I3->O            5   0.648   0.713  _and000012 (N32)
     LUT2:I1->O           32   0.643   1.262  wb_interface/pulsewidth_and00001 (wb_interface/pulsewidth_and0000)
     FDCE_1:CE                 0.312          wb_interface/pulsewidth_0
    ----------------------------------------
    Total                      7.398ns (3.743ns logic, 3.655ns route)
                                       (50.6% logic, 49.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'wb_clk_i'
  Total number of paths / destination ports: 96 / 37
-------------------------------------------------------------------------
Offset:              7.061ns (Levels of Logic = 3)
  Source:            wb_interface/p2p_8 (FF)
  Destination:       wb_dat_o<8> (PAD)
  Source Clock:      wb_clk_i falling

  Data Path: wb_interface/p2p_8 to wb_dat_o<8>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE_1:C->Q           3   0.591   0.611  wb_interface/p2p_8 (wb_interface/p2p_8)
     LUT4:I1->O            1   0.643   0.000  wb_interface/Mmux_wb_dat_rdbk401 (wb_interface/Mmux_wb_dat_rdbk40)
     MUXF5:I1->O           1   0.276   0.420  wb_interface/Mmux_wb_dat_rdbk40_f5 (wb_interface/wb_dat_rdbk<8>)
     OBUFT:I->O                4.520          wb_dat_o_8_OBUFT (wb_dat_o<8>)
    ----------------------------------------
    Total                      7.061ns (6.030ns logic, 1.031ns route)
                                       (85.4% logic, 14.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 342 / 32
-------------------------------------------------------------------------
Delay:               9.636ns (Levels of Logic = 6)
  Source:            wb_adr_i<1> (PAD)
  Destination:       wb_dat_o<8> (PAD)

  Data Path: wb_adr_i<1> to wb_dat_o<8>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.849   0.590  wb_adr_i_1_IBUF (wb_adr_i_1_IBUF)
     LUT4:I0->O            1   0.648   0.000  wb_interface/Mmux_wb_dat_rdbk1411 (wb_interface/Mmux_wb_dat_rdbk1411)
     MUXF5:I0->O          43   0.276   1.409  wb_interface/Mmux_wb_dat_rdbk141_f5 (N01)
     LUT4:I0->O            1   0.648   0.000  wb_interface/Mmux_wb_dat_rdbk401 (wb_interface/Mmux_wb_dat_rdbk40)
     MUXF5:I1->O           1   0.276   0.420  wb_interface/Mmux_wb_dat_rdbk40_f5 (wb_interface/wb_dat_rdbk<8>)
     OBUFT:I->O                4.520          wb_dat_o_8_OBUFT (wb_dat_o<8>)
    ----------------------------------------
    Total                      9.636ns (7.217ns logic, 2.419ns route)
                                       (74.9% logic, 25.1% route)

=========================================================================


Total REAL time to Xst completion: 7.00 secs
Total CPU time to Xst completion: 7.14 secs
 
--> 

Total memory usage is 287180 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    0 (   0 filtered)