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[/] [wiegand_ctl/] [trunk/] [syn/] [xilinx/] [wiegand_tx/] [ise/] [wiegand_tx_top/] [wiegand_tx_top.twr] - Rev 17
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--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml wiegand_tx_top.twx wiegand_tx_top.ncd -o
wiegand_tx_top.twr wiegand_tx_top.pcf -ucf wiegand_tx_top.ucf
Design file: wiegand_tx_top.ncd
Physical constraint file: wiegand_tx_top.pcf
Device,package,speed: xc3s700an,fgg484,-4 (PRODUCTION 1.42 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
================================================================================
Timing constraint: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
3668 paths analyzed, 850 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 16.516ns.
--------------------------------------------------------------------------------
Paths for end point state_FSM_FFd3 (SLICE_X10Y64.F4), 47 paths
--------------------------------------------------------------------------------
Slack (setup path): 1.742ns (requirement - (data path - clock path skew + uncertainty))
Source: wb_interface/p2p_1 (FF)
Destination: state_FSM_FFd3 (FF)
Requirement: 10.000ns
Data Path Delay: 8.106ns (Levels of Logic = 10)
Clock Path Skew: -0.152ns (0.403 - 0.555)
Source Clock: wb_clk_i_BUFGP falling at 10.000ns
Destination Clock: wb_clk_i_BUFGP rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: wb_interface/p2p_1 to state_FSM_FFd3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X3Y80.XQ Tcko 0.591 wb_interface/p2p<1>
wb_interface/p2p_1
SLICE_X3Y48.F3 net (fanout=3) 1.940 wb_interface/p2p<1>
SLICE_X3Y48.COUT Topcyf 1.195 Mcompar_state_cmp_eq0001_cy<1>
Mcompar_state_cmp_eq0001_lut<0>
Mcompar_state_cmp_eq0001_cy<0>
Mcompar_state_cmp_eq0001_cy<1>
SLICE_X3Y49.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<1>
SLICE_X3Y49.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<3>
Mcompar_state_cmp_eq0001_cy<2>
Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<5>
Mcompar_state_cmp_eq0001_cy<4>
Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<7>
Mcompar_state_cmp_eq0001_cy<6>
Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<9>
Mcompar_state_cmp_eq0001_cy<8>
Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<11>
Mcompar_state_cmp_eq0001_cy<10>
Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<13>
Mcompar_state_cmp_eq0001_cy<12>
Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<15>
Mcompar_state_cmp_eq0001_cy<14>
Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.G4 net (fanout=2) 1.901 Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.Y Tilo 0.707 state_FSM_FFd3
state_FSM_FFd3-In74
SLICE_X10Y64.F4 net (fanout=1) 0.060 state_FSM_FFd3-In74/O
SLICE_X10Y64.CLK Tfck 0.802 state_FSM_FFd3
state_FSM_FFd3-In87
state_FSM_FFd3
------------------------------------------------- ---------------------------
Total 8.106ns (4.205ns logic, 3.901ns route)
(51.9% logic, 48.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.845ns (requirement - (data path - clock path skew + uncertainty))
Source: wb_interface/p2p_3 (FF)
Destination: state_FSM_FFd3 (FF)
Requirement: 10.000ns
Data Path Delay: 7.986ns (Levels of Logic = 10)
Clock Path Skew: -0.169ns (0.403 - 0.572)
Source Clock: wb_clk_i_BUFGP falling at 10.000ns
Destination Clock: wb_clk_i_BUFGP rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: wb_interface/p2p_3 to state_FSM_FFd3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X2Y75.XQ Tcko 0.631 wb_interface/p2p<3>
wb_interface/p2p_3
SLICE_X3Y48.G4 net (fanout=3) 1.797 wb_interface/p2p<3>
SLICE_X3Y48.COUT Topcyg 1.178 Mcompar_state_cmp_eq0001_cy<1>
Mcompar_state_cmp_eq0001_lut<1>
Mcompar_state_cmp_eq0001_cy<1>
SLICE_X3Y49.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<1>
SLICE_X3Y49.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<3>
Mcompar_state_cmp_eq0001_cy<2>
Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<5>
Mcompar_state_cmp_eq0001_cy<4>
Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<7>
Mcompar_state_cmp_eq0001_cy<6>
Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<9>
Mcompar_state_cmp_eq0001_cy<8>
Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<11>
Mcompar_state_cmp_eq0001_cy<10>
Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<13>
Mcompar_state_cmp_eq0001_cy<12>
Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<15>
Mcompar_state_cmp_eq0001_cy<14>
Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.G4 net (fanout=2) 1.901 Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.Y Tilo 0.707 state_FSM_FFd3
state_FSM_FFd3-In74
SLICE_X10Y64.F4 net (fanout=1) 0.060 state_FSM_FFd3-In74/O
SLICE_X10Y64.CLK Tfck 0.802 state_FSM_FFd3
state_FSM_FFd3-In87
state_FSM_FFd3
------------------------------------------------- ---------------------------
Total 7.986ns (4.228ns logic, 3.758ns route)
(52.9% logic, 47.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 1.918ns (requirement - (data path - clock path skew + uncertainty))
Source: wb_interface/p2p_5 (FF)
Destination: state_FSM_FFd3 (FF)
Requirement: 10.000ns
Data Path Delay: 7.917ns (Levels of Logic = 9)
Clock Path Skew: -0.165ns (0.403 - 0.568)
Source Clock: wb_clk_i_BUFGP falling at 10.000ns
Destination Clock: wb_clk_i_BUFGP rising at 20.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: wb_interface/p2p_5 to state_FSM_FFd3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X3Y76.XQ Tcko 0.591 wb_interface/p2p<5>
wb_interface/p2p_5
SLICE_X3Y49.F1 net (fanout=3) 1.881 wb_interface/p2p<5>
SLICE_X3Y49.COUT Topcyf 1.195 Mcompar_state_cmp_eq0001_cy<3>
Mcompar_state_cmp_eq0001_lut<2>
Mcompar_state_cmp_eq0001_cy<2>
Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<3>
SLICE_X3Y50.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<5>
Mcompar_state_cmp_eq0001_cy<4>
Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<5>
SLICE_X3Y51.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<7>
Mcompar_state_cmp_eq0001_cy<6>
Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<7>
SLICE_X3Y52.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<9>
Mcompar_state_cmp_eq0001_cy<8>
Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<9>
SLICE_X3Y53.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<11>
Mcompar_state_cmp_eq0001_cy<10>
Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<11>
SLICE_X3Y54.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<13>
Mcompar_state_cmp_eq0001_cy<12>
Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.CIN net (fanout=1) 0.000 Mcompar_state_cmp_eq0001_cy<13>
SLICE_X3Y55.COUT Tbyp 0.130 Mcompar_state_cmp_eq0001_cy<15>
Mcompar_state_cmp_eq0001_cy<14>
Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.G4 net (fanout=2) 1.901 Mcompar_state_cmp_eq0001_cy<15>
SLICE_X10Y64.Y Tilo 0.707 state_FSM_FFd3
state_FSM_FFd3-In74
SLICE_X10Y64.F4 net (fanout=1) 0.060 state_FSM_FFd3-In74/O
SLICE_X10Y64.CLK Tfck 0.802 state_FSM_FFd3
state_FSM_FFd3-In87
state_FSM_FFd3
------------------------------------------------- ---------------------------
Total 7.917ns (4.075ns logic, 3.842ns route)
(51.5% logic, 48.5% route)
--------------------------------------------------------------------------------
Paths for end point datafifowrite/custom_fifo_dp6/addr_rd_1 (SLICE_X11Y0.CE), 8 paths
--------------------------------------------------------------------------------
Slack (setup path): 2.087ns (requirement - (data path - clock path skew + uncertainty))
Source: state_FSM_FFd2 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
Requirement: 10.000ns
Data Path Delay: 7.836ns (Levels of Logic = 2)
Clock Path Skew: -0.077ns (0.561 - 0.638)
Source Clock: wb_clk_i_BUFGP rising at 0.000ns
Destination Clock: wb_clk_i_BUFGP falling at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: state_FSM_FFd2 to datafifowrite/custom_fifo_dp6/addr_rd_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X10Y65.XQ Tcko 0.631 state_FSM_FFd2
state_FSM_FFd2
SLICE_X6Y51.G3 net (fanout=87) 2.122 state_FSM_FFd2
SLICE_X6Y51.Y Tilo 0.707 datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
word_out_mux0000<10>11
SLICE_X11Y1.F2 net (fanout=8) 2.479 N4
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_1
------------------------------------------------- ---------------------------
Total 7.836ns (2.292ns logic, 5.544ns route)
(29.2% logic, 70.8% route)
--------------------------------------------------------------------------------
Slack (setup path): 2.517ns (requirement - (data path - clock path skew + uncertainty))
Source: state_FSM_FFd3 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
Requirement: 10.000ns
Data Path Delay: 7.406ns (Levels of Logic = 2)
Clock Path Skew: -0.077ns (0.561 - 0.638)
Source Clock: wb_clk_i_BUFGP rising at 0.000ns
Destination Clock: wb_clk_i_BUFGP falling at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: state_FSM_FFd3 to datafifowrite/custom_fifo_dp6/addr_rd_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X10Y64.XQ Tcko 0.631 state_FSM_FFd3
state_FSM_FFd3
SLICE_X6Y51.G2 net (fanout=86) 1.692 state_FSM_FFd3
SLICE_X6Y51.Y Tilo 0.707 datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
word_out_mux0000<10>11
SLICE_X11Y1.F2 net (fanout=8) 2.479 N4
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_1
------------------------------------------------- ---------------------------
Total 7.406ns (2.292ns logic, 5.114ns route)
(30.9% logic, 69.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 15.134ns (requirement - (data path - clock path skew + uncertainty))
Source: datafifowrite/custom_fifo_dp6/addr_wr_1 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_1 (FF)
Requirement: 20.000ns
Data Path Delay: 4.820ns (Levels of Logic = 2)
Clock Path Skew: -0.046ns (0.212 - 0.258)
Source Clock: wb_clk_i_BUFGP falling at 10.000ns
Destination Clock: wb_clk_i_BUFGP falling at 30.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: datafifowrite/custom_fifo_dp6/addr_wr_1 to datafifowrite/custom_fifo_dp6/addr_rd_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X7Y4.XQ Tcko 0.591 datafifowrite/custom_fifo_dp6/addr_wr<1>
datafifowrite/custom_fifo_dp6/addr_wr_1
SLICE_X9Y0.F2 net (fanout=8) 1.221 datafifowrite/custom_fifo_dp6/addr_wr<1>
SLICE_X9Y0.X Tilo 0.643 N125
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000_SW0
SLICE_X11Y1.F1 net (fanout=1) 0.468 N125
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_1
------------------------------------------------- ---------------------------
Total 4.820ns (2.188ns logic, 2.632ns route)
(45.4% logic, 54.6% route)
--------------------------------------------------------------------------------
Paths for end point datafifowrite/custom_fifo_dp6/addr_rd_0 (SLICE_X11Y0.CE), 8 paths
--------------------------------------------------------------------------------
Slack (setup path): 2.087ns (requirement - (data path - clock path skew + uncertainty))
Source: state_FSM_FFd2 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
Requirement: 10.000ns
Data Path Delay: 7.836ns (Levels of Logic = 2)
Clock Path Skew: -0.077ns (0.561 - 0.638)
Source Clock: wb_clk_i_BUFGP rising at 0.000ns
Destination Clock: wb_clk_i_BUFGP falling at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: state_FSM_FFd2 to datafifowrite/custom_fifo_dp6/addr_rd_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X10Y65.XQ Tcko 0.631 state_FSM_FFd2
state_FSM_FFd2
SLICE_X6Y51.G3 net (fanout=87) 2.122 state_FSM_FFd2
SLICE_X6Y51.Y Tilo 0.707 datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
word_out_mux0000<10>11
SLICE_X11Y1.F2 net (fanout=8) 2.479 N4
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_0
------------------------------------------------- ---------------------------
Total 7.836ns (2.292ns logic, 5.544ns route)
(29.2% logic, 70.8% route)
--------------------------------------------------------------------------------
Slack (setup path): 2.517ns (requirement - (data path - clock path skew + uncertainty))
Source: state_FSM_FFd3 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
Requirement: 10.000ns
Data Path Delay: 7.406ns (Levels of Logic = 2)
Clock Path Skew: -0.077ns (0.561 - 0.638)
Source Clock: wb_clk_i_BUFGP rising at 0.000ns
Destination Clock: wb_clk_i_BUFGP falling at 10.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: state_FSM_FFd3 to datafifowrite/custom_fifo_dp6/addr_rd_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X10Y64.XQ Tcko 0.631 state_FSM_FFd3
state_FSM_FFd3
SLICE_X6Y51.G2 net (fanout=86) 1.692 state_FSM_FFd3
SLICE_X6Y51.Y Tilo 0.707 datafifowrite/custom_fifo_dp8/addr_rd_2_and0000
word_out_mux0000<10>11
SLICE_X11Y1.F2 net (fanout=8) 2.479 N4
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_0
------------------------------------------------- ---------------------------
Total 7.406ns (2.292ns logic, 5.114ns route)
(30.9% logic, 69.1% route)
--------------------------------------------------------------------------------
Slack (setup path): 15.134ns (requirement - (data path - clock path skew + uncertainty))
Source: datafifowrite/custom_fifo_dp6/addr_wr_1 (FF)
Destination: datafifowrite/custom_fifo_dp6/addr_rd_0 (FF)
Requirement: 20.000ns
Data Path Delay: 4.820ns (Levels of Logic = 2)
Clock Path Skew: -0.046ns (0.212 - 0.258)
Source Clock: wb_clk_i_BUFGP falling at 10.000ns
Destination Clock: wb_clk_i_BUFGP falling at 30.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: datafifowrite/custom_fifo_dp6/addr_wr_1 to datafifowrite/custom_fifo_dp6/addr_rd_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X7Y4.XQ Tcko 0.591 datafifowrite/custom_fifo_dp6/addr_wr<1>
datafifowrite/custom_fifo_dp6/addr_wr_1
SLICE_X9Y0.F2 net (fanout=8) 1.221 datafifowrite/custom_fifo_dp6/addr_wr<1>
SLICE_X9Y0.X Tilo 0.643 N125
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000_SW0
SLICE_X11Y1.F1 net (fanout=1) 0.468 N125
SLICE_X11Y1.X Tilo 0.643 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CE net (fanout=2) 0.943 datafifowrite/custom_fifo_dp6/addr_rd_2_and0000
SLICE_X11Y0.CLK Tceck 0.311 datafifowrite/custom_fifo_dp6/addr_rd<1>
datafifowrite/custom_fifo_dp6/addr_rd_0
------------------------------------------------- ---------------------------
Total 4.820ns (2.188ns logic, 2.632ns route)
(45.4% logic, 54.6% route)
--------------------------------------------------------------------------------
Hold Paths: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Paths for end point datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7 (SLICE_X2Y23.CE), 1 path
--------------------------------------------------------------------------------
Slack (hold path): 0.975ns (requirement - (clock path skew + uncertainty - data path))
Source: datafifowrite/custom_fifo_dp7/addr_wr_1 (FF)
Destination: datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7 (FF)
Requirement: 0.000ns
Data Path Delay: 1.147ns (Levels of Logic = 0)
Clock Path Skew: 0.172ns (0.626 - 0.454)
Source Clock: wb_clk_i_BUFGP falling at 30.000ns
Destination Clock: wb_clk_i_BUFGP falling at 30.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: datafifowrite/custom_fifo_dp7/addr_wr_1 to datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X2Y26.XQ Tcko 0.505 datafifowrite/custom_fifo_dp7/addr_wr<1>
datafifowrite/custom_fifo_dp7/addr_wr_1
SLICE_X2Y23.CE net (fanout=8) 0.642 datafifowrite/custom_fifo_dp7/addr_wr<1>
SLICE_X2Y23.CLK Tckce (-Th) 0.000 datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg<7>
datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_7
------------------------------------------------- ---------------------------
Total 1.147ns (0.505ns logic, 0.642ns route)
(44.0% logic, 56.0% route)
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Paths for end point datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6 (SLICE_X2Y23.CE), 1 path
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Slack (hold path): 0.975ns (requirement - (clock path skew + uncertainty - data path))
Source: datafifowrite/custom_fifo_dp7/addr_wr_1 (FF)
Destination: datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6 (FF)
Requirement: 0.000ns
Data Path Delay: 1.147ns (Levels of Logic = 0)
Clock Path Skew: 0.172ns (0.626 - 0.454)
Source Clock: wb_clk_i_BUFGP falling at 30.000ns
Destination Clock: wb_clk_i_BUFGP falling at 30.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: datafifowrite/custom_fifo_dp7/addr_wr_1 to datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X2Y26.XQ Tcko 0.505 datafifowrite/custom_fifo_dp7/addr_wr<1>
datafifowrite/custom_fifo_dp7/addr_wr_1
SLICE_X2Y23.CE net (fanout=8) 0.642 datafifowrite/custom_fifo_dp7/addr_wr<1>
SLICE_X2Y23.CLK Tckce (-Th) 0.000 datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg<7>
datafifowrite/custom_fifo_dp7/mem[1].mem_byte/byte_reg_6
------------------------------------------------- ---------------------------
Total 1.147ns (0.505ns logic, 0.642ns route)
(44.0% logic, 56.0% route)
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Paths for end point datafifowrite/custom_fifo_dp8/addr_wr_0 (SLICE_X0Y51.BY), 1 path
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Slack (hold path): 1.015ns (requirement - (clock path skew + uncertainty - data path))
Source: datafifowrite/custom_fifo_dp8/addr_wr_2 (FF)
Destination: datafifowrite/custom_fifo_dp8/addr_wr_0 (FF)
Requirement: 0.000ns
Data Path Delay: 1.031ns (Levels of Logic = 0)
Clock Path Skew: 0.016ns (0.110 - 0.094)
Source Clock: wb_clk_i_BUFGP falling at 30.000ns
Destination Clock: wb_clk_i_BUFGP falling at 30.000ns
Clock Uncertainty: 0.000ns
Minimum Data Path: datafifowrite/custom_fifo_dp8/addr_wr_2 to datafifowrite/custom_fifo_dp8/addr_wr_0
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X1Y50.YQ Tcko 0.464 datafifowrite/custom_fifo_dp8/addr_wr<2>
datafifowrite/custom_fifo_dp8/addr_wr_2
SLICE_X0Y51.BY net (fanout=8) 0.394 datafifowrite/custom_fifo_dp8/addr_wr<2>
SLICE_X0Y51.CLK Tckdi (-Th) -0.173 datafifowrite/custom_fifo_dp8/addr_wr<1>
datafifowrite/custom_fifo_dp8/addr_wr_0
------------------------------------------------- ---------------------------
Total 1.031ns (0.637ns logic, 0.394ns route)
(61.8% logic, 38.2% route)
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Component Switching Limit Checks: TS_wb_clk_i = PERIOD TIMEGRP "wb_clk_i" 20 ns HIGH 50%;
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Slack: 16.796ns (period - (min low pulse limit / (low pulse / period)))
Period: 20.000ns
Low pulse: 10.000ns
Low pulse limit: 1.602ns (Trpw)
Physical resource: state_FSM_FFd2/SR
Logical resource: state_FSM_FFd2/SR
Location pin: SLICE_X10Y65.SR
Clock network: wb_rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 16.796ns (period - (min high pulse limit / (high pulse / period)))
Period: 20.000ns
High pulse: 10.000ns
High pulse limit: 1.602ns (Trpw)
Physical resource: state_FSM_FFd2/SR
Logical resource: state_FSM_FFd2/SR
Location pin: SLICE_X10Y65.SR
Clock network: wb_rst_i_IBUF
--------------------------------------------------------------------------------
Slack: 16.796ns (period - (min low pulse limit / (low pulse / period)))
Period: 20.000ns
Low pulse: 10.000ns
Low pulse limit: 1.602ns (Trpw)
Physical resource: wb_interface/ack/SR
Logical resource: wb_interface/ack/SR
Location pin: SLICE_X0Y76.SR
Clock network: wb_rst_i_IBUF
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All constraints were met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock wb_clk_i
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wb_clk_i | 9.531| 8.258| 7.913| 8.557|
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)
Constraints cover 3668 paths, 0 nets, and 1308 connections
Design statistics:
Minimum period: 16.516ns{1} (Maximum frequency: 60.547MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Mon Feb 16 11:08:59 2015
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Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 195 MB