OpenCores
URL https://opencores.org/ocsvn/xucpu/xucpu/trunk

Subversion Repositories xucpu

[/] [xucpu/] [trunk/] [src/] [components/] [BRAM/] [Makefile] - Rev 22

Go to most recent revision | Compare with Previous | Blame | View Log

GHDL:=/opt/ghdl/ghdl_mcode/translate/ghdldrv/ghdl_mcode

SOURCE:= ../../util/file/hexio.vhdl \
        ../../components/multiplexer/MUX.vhdl \
        generic_memory_block.vhdl \
        ram_parts.vhdl \
        RAM.vhdl \
        tb_generic_ram.vhdl

tb_generic:
        $(GHDL) -a $(SOURCE)
        $(GHDL) -e tb_generic_ram

# vim: set tw=0:

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.