Subversion Repositories xucpu

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY cache_block IS
 
  -- Cache memory block of 512x16
  GENERIC (
    w_data    : NATURAL RANGE 1 TO 32 := 16;
    w_addr    : NATURAL RANGE 8 TO 14 := 9);
  PORT (
    clk : IN  STD_LOGIC;
    we  : IN  STD_LOGIC;
    a1  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Data port address
    a2  : IN  STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);  -- Instruction port address
    d1  : IN  STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port input
    q1  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0);  -- Data port output
    q2  : OUT STD_LOGIC_VECTOR(w_data - 1 DOWNTO 0));  -- Instruction port output
 
END cache_block;
 
ARCHITECTURE Behavioral OF cache_block IS
 
  SIGNAL address_reg_1 : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
  SIGNAL address_reg_2 : STD_LOGIC_VECTOR(w_addr - 1 DOWNTO 0);
 
BEGIN  -- Behavioral
 
  -- purpose: Try to describe a proper block ram without needing to instantiate a BRAM
  -- type   : sequential
  -- inputs : clk, we, a1, a2, d1
  -- outputs: q1, q2
  MP1 : PROCESS (clk, address_reg_1, address_reg_2, mem)
  BEGIN  -- PROCESS MP1
 
    -- Reading
    q1 <= STD_LOGIC_VECTOR(to_unsigned(mem(to_integer(UNSIGNED(address_reg_1))), w_data));
    q2 <= STD_LOGIC_VECTOR(to_unsigned(mem(to_integer(UNSIGNED(address_reg_2))), w_data));
    IF rising_edge(clk) THEN            -- rising clock edge
 
      -- These work like the block RAM registers
      address_reg_1 <= a1;
      address_reg_2 <= a2;
 
      -- Writing
      IF we = '1' THEN
        mem(to_integer(UNSIGNED(a1))) <= to_integer(UNSIGNED(d1));
      END IF;
 
    END IF;
 
  END PROCESS MP1;
 
END Behavioral;