Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

#######################################################################
##      File: altera_jtag_uart.IP
##    
##      Copyright (C) 2014-2019  Alireza Monemi
##    
##      This file is part of ProNoC 2.0.0 
##
##      WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT 
##      MAY CAUSE UNEXPECTED BEHAIVOR.
################################################################################

$ipgen = bless( {
                  'parameters_order' => [
                                          'SIM_BUFFER_SIZE',
                                          'SIM_WAIT_COUNT',
                                          'INCLUDE_SIM_PRINTF'
                                        ],
                  'ip_name' => 'altera_jtag_uart',
                  'modules' => {
                                 'altera_jtag_uart' => {}
                               },
                  'system_h' => '

#define ${IP}_DATA_REG                                  (*((volatile unsigned int *) ($BASE)))
#define ${IP}_CONTROL_REG                               (*((volatile unsigned int *) ($BASE+4)))
#define ${IP}_CONTROL_WSPACE_MSK        0xFFFF0000
#define ${IP}_DATA_RVALID_MSK                   0x00008000
#define ${IP}_DATA_DATA_MSK                     0x000000FF

//////////////////////////////*basic function for jtag_uart*////////////////////////////////////////
void jtag_putchar(char ch);
char jtag_getchar(void);
void outbyte(char c); //called in printf();
char inbyte(void);
void jtag_putchar(char ch);
char jtag_getchar(void);
int jtag_scanstr(char* buf);
int jtag_scanint(int *num);
/////////////////////////////*END: basic function for jtag_uart*////////////////////////////////////

#define INCLUDE_${INCLUDE_SIM_PRINTF}

#ifdef INCLUDE_SIMPLE_PRINTF
        #include "simple-printf/printf.h" 
#endif

#ifdef INCLUDE_SIMPLE_PRINTF_LONG
        #include "simple-printf/printf.h" 
#endif',
                  'file_name' => 'mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
                  'module_name' => 'altera_jtag_uart',
                  'ports' => {
                               's_cyc_i' => {
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'range' => '',
                                              'type' => 'input',
                                              'intfc_port' => 'cyc_i'
                                            },
                               's_cti_i' => {
                                              'range' => '2    :   0',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'cti_i',
                                              'type' => 'input'
                                            },
                               's_dat_i' => {
                                              'intfc_port' => 'dat_i',
                                              'type' => 'input',
                                              'range' => '31       :   0',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               'RxD_wr_sim' => {
                                                 'intfc_port' => 'RxD_wr_sim',
                                                 'type' => 'input',
                                                 'range' => '',
                                                 'intfc_name' => 'socket:RxD_sim[0]'
                                               },
                               's_we_i' => {
                                             'intfc_port' => 'we_i',
                                             'type' => 'input',
                                             'range' => '',
                                             'intfc_name' => 'plug:wb_slave[0]'
                                           },
                               'RxD_din_sim' => {
                                                  'intfc_port' => 'RxD_din_sim',
                                                  'type' => 'input',
                                                  'range' => '7:0 ',
                                                  'intfc_name' => 'socket:RxD_sim[0]'
                                                },
                               'clk' => {
                                          'intfc_port' => 'clk_i',
                                          'type' => 'input',
                                          'range' => '',
                                          'intfc_name' => 'plug:clk[0]'
                                        },
                               's_stb_i' => {
                                              'intfc_port' => 'stb_i',
                                              'type' => 'input',
                                              'range' => '',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               'reset' => {
                                            'intfc_port' => 'reset_i',
                                            'type' => 'input',
                                            'range' => '',
                                            'intfc_name' => 'plug:reset[0]'
                                          },
                               's_addr_i' => {
                                               'range' => '',
                                               'intfc_name' => 'plug:wb_slave[0]',
                                               'intfc_port' => 'adr_i',
                                               'type' => 'input'
                                             },
                               'irq' => {
                                          'range' => '',
                                          'intfc_name' => 'plug:interrupt_peripheral[0]',
                                          'intfc_port' => 'int_o',
                                          'type' => 'output'
                                        },
                               's_dat_o' => {
                                              'range' => '31      :   0',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'dat_o',
                                              'type' => 'output'
                                            },
                               'RxD_ready_sim' => {
                                                    'type' => 'output',
                                                    'intfc_port' => 'RxD_ready_sim',
                                                    'intfc_name' => 'socket:RxD_sim[0]',
                                                    'range' => ''
                                                  },
                               's_sel_i' => {
                                              'intfc_port' => 'sel_i',
                                              'type' => 'input',
                                              'range' => '3    :   0',
                                              'intfc_name' => 'plug:wb_slave[0]'
                                            },
                               's_ack_o' => {
                                              'range' => '',
                                              'intfc_name' => 'plug:wb_slave[0]',
                                              'intfc_port' => 'ack_o',
                                              'type' => 'output'
                                            }
                             },
                  'sw_files' => [
                                  '/mpsoc/src_processor/src_lib/simple-printf'
                                ],
                  'gui_status' => {
                                    'timeout' => 0,
                                    'status' => 'ideal'
                                  },
                  'system_c' => '

void outbyte(char c){jtag_putchar(c);} //called in printf();

char inbyte(){return jtag_getchar();}

void jtag_putchar(char ch){ //print one char from jtag_uart
        while((${IP}_CONTROL_REG&${IP}_CONTROL_WSPACE_MSK)==0);
        ${IP}_DATA_REG=ch;
}

char jtag_getchar(void){ //get one char from jtag_uart
        unsigned int data;
        data=${IP}_DATA_REG;
        while(!(data & ${IP}_DATA_RVALID_MSK)) //wait for terminal input
                data=${IP}_DATA_REG;
        return (data & ${IP}_DATA_DATA_MSK);
}       

int jtag_scanstr(char* buf){ //scan string until <ENTER> to buf, return str length 
        char ch; unsigned int i=0;
        while(1){
                ch=jtag_getchar();
                if(ch==\'\\n\') { buf[i]=0; jtag_putchar(ch); i++; break; } //ENTER
                else if(ch==127) { printf("\\b \\b"); if(i>0) i--; } //backspace
                else { jtag_putchar(ch); buf[i]=ch; i++; } //valid
        }
        return i;
}

int jtag_scanint(int *num){ //return the scanned integer
        unsigned int curr_num,strlen,i=0;
        char str[11];
        strlen=jtag_scanstr(str); //scan str
        if(strlen>11) { printf("overflows 32-bit integer value\\n");return 1; } //check overflow
        *num=0;
        for(i=0;i<strlen;i++){ //str2int
                curr_num=(unsigned int)str[i]-\'0\';
                if(curr_num>9); //not integer: do nothing
                else *num=*num*10+curr_num;  //is integer
        }
        return 0;
}

#ifdef INCLUDE_SIMPLE_PRINTF
        #include "simple-printf/printf.c" 
#endif

#ifdef INCLUDE_SIMPLE_PRINTF_LONG
        #include "simple-printf/prinf_long.c" 
#endif


',
                  'category' => 'Communication',
                  'parameters' => {
                                    'SIM_WAIT_COUNT' => {
                                                          'global_param' => 'Localparam',
                                                          'info' => 'This parameter is valid only in simulation. 
If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.',
                                                          'content' => '2,100000,1',
                                                          'redefine_param' => 1,
                                                          'default' => '1000',
                                                          'type' => 'Spin-button'
                                                        },
                                    'SIM_BUFFER_SIZE' => {
                                                           'info' => 'Internal buffer size. 
This parameter is valid only in simulation. 
If internal buffer overflows, the buffer content are displayed on simulator terminal.',
                                                           'content' => '10,10000,1',
                                                           'global_param' => 'Localparam',
                                                           'type' => 'Spin-button',
                                                           'default' => '100',
                                                           'redefine_param' => 1
                                                         },
                                    'INCLUDE_SIM_PRINTF' => {
                                                              'info' => 'Select source code for printf command:
    "NONE":  Do not include simple_printf source code. Select "NONE" In case printf command is supported in <stdio.h>, or it is not needed in the software code. 
    "SIMPLE_PRINTF" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, and %%s. long and floating formats are not supported.
    "SIMPLE_PRINTF_LONG" Include a source code of printf command which supports a subset of formatted data: %%d, %%i, %%u, %%x, %%c, %%l, and %%s.  floating format is not supported.
        ',
                                                              'content' => 'NONE,SIMPLE_PRINTF,SIMPLE_PRINTF_LONG',
                                                              'global_param' => 'Don\'t include',
                                                              'redefine_param' => 0,
                                                              'default' => 'SIMPLE_PRINTF',
                                                              'type' => 'Combo-box'
                                                            },
                                    
                                  },
                  'ports_order' => [
                                     'reset',
                                     'clk',
                                     'irq',
                                     's_dat_i',
                                     's_sel_i',
                                     's_addr_i',
                                     's_cti_i',
                                     's_stb_i',
                                     's_cyc_i',
                                     's_we_i',
                                     's_dat_o',
                                     's_ack_o',
                                     'RxD_din_sim',
                                     'RxD_wr_sim',
                                     'RxD_ready_sim'
                                   ],
                  'description' => 'The Altera JTAG UART IP core (qsys_jtag_uart) with Wishbone bus interface.',
                  'version' => 20,
                  'unused' => {
                                'plug:wb_slave[0]' => [
                                                        'tag_i',
                                                        'bte_i',
                                                        'rty_o',
                                                        'err_o'
                                                      ]
                              },
                  'sockets' => {
                                 'RxD_sim' => {
                                                'connection_num' => 'single connection',
                                                'value' => 1,
                                                'type' => 'num',
                                                '0' => {
                                                         'name' => 'RxD_sim'
                                                       }
                                              }
                               },
                  'plugs' => {
                               'interrupt_peripheral' => {
                                                           'value' => 1,
                                                           'type' => 'num',
                                                           '0' => {
                                                                    'name' => 'interrupt_peripheral'
                                                                  }
                                                         },
                               'reset' => {
                                            'value' => 1,
                                            'type' => 'num',
                                            '0' => {
                                                     'name' => 'reset'
                                                   }
                                          },
                               'clk' => {
                                          'value' => 1,
                                          'type' => 'num',
                                          '0' => {
                                                   'name' => 'clk'
                                                 }
                                        },
                               'wb_slave' => {
                                               'value' => 1,
                                               'type' => 'num',
                                               '0' => {
                                                        'addr' => '0x9000_0000  0x90ff_ffff             UART16550 Controller',
                                                        'width' => 5,
                                                        'name' => 'wb_slave'
                                                      }
                                             }
                             },
                  'hdl_files' => [
                                   '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_jtag_uart.v',
                                   '/mpsoc/rtl/src_peripheral/jtag/jtag_uart/altera_uart_simulator.v'
                                 ]
                }, 'ip_gen' );