URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [Processor/] [lm32.IP] - Rev 38
Go to most recent revision | Compare with Previous | Blame | View Log
######################################################################### File: lm32.IP#### Copyright (C) 2014-2016 Alireza Monemi#### This file is part of ProNoC 1.7.0#### WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT## MAY CAUSE UNEXPECTED BEHAIVOR.################################################################################$lm32 = bless( {'hdl_files' => ['/mpsoc/src_processor/lm32/verilog/src/er1.v','/mpsoc/src_processor/lm32/verilog/src/JTAGB.v','/mpsoc/src_processor/lm32/verilog/src/jtag_lm32.v','/mpsoc/src_processor/lm32/verilog/src/lm32.v','/mpsoc/src_processor/lm32/verilog/src/lm32_adder.v','/mpsoc/src_processor/lm32/verilog/src/lm32_addsub.v','/mpsoc/src_processor/lm32/verilog/src/lm32_cpu.v','/mpsoc/src_processor/lm32/verilog/src/lm32_dcache.v','/mpsoc/src_processor/lm32/verilog/src/lm32_debug.v','/mpsoc/src_processor/lm32/verilog/src/lm32_decoder.v','/mpsoc/src_processor/lm32/verilog/src/lm32_functions.v','/mpsoc/src_processor/lm32/verilog/src/lm32_icache.v','/mpsoc/src_processor/lm32/verilog/src/lm32_include.v','/mpsoc/src_processor/lm32/verilog/src/lm32_instruction_unit.v','/mpsoc/src_processor/lm32/verilog/src/lm32_interrupt.v','/mpsoc/src_processor/lm32/verilog/src/lm32_jtag.v','/mpsoc/src_processor/lm32/verilog/src/lm32_load_store_unit.v','/mpsoc/src_processor/lm32/verilog/src/lm32_logic_op.v','/mpsoc/src_processor/lm32/verilog/src/lm32_mc_arithmetic.v','/mpsoc/src_processor/lm32/verilog/src/lm32_monitor.v','/mpsoc/src_processor/lm32/verilog/src/lm32_multiplier.v','/mpsoc/src_processor/lm32/verilog/src/lm32_ram.v','/mpsoc/src_processor/lm32/verilog/src/lm32_shifter.v','/mpsoc/src_processor/lm32/verilog/src/lm32_simtrace.v','/mpsoc/src_processor/lm32/verilog/src/lm32_top.v','/mpsoc/src_processor/lm32/verilog/src/spiprog.v','/mpsoc/src_processor/lm32/verilog/src/system_conf.v','/mpsoc/src_processor/lm32/verilog/src/typea.v','/mpsoc/src_processor/lm32/verilog/src/typeb.v'],'category' => 'Processor','sockets' => {'interrupt_peripheral' => {'type' => 'param','interrupt_peripheral' => {},'0' => {'name' => 'interrupt_peripheral'},'value' => 'INTR_NUM','connection_num' => 'single connection'}},'sw_files' => ['/mpsoc/src_processor/lm32/sw/crt0ram.S','/mpsoc/src_processor/lm32/sw/linker.ld','/mpsoc/src_processor/lm32/sw/lm32_system.h','/mpsoc/src_processor/lm32/sw/Makefile','/mpsoc/src_processor/lm32/sw/program','/mpsoc/src_processor/program.sh','/mpsoc/src_processor/lm32/sw/define_printf.h','/mpsoc/src_processor/src_lib/simple-printf'],'unused' => {'plug:wb_master[0]' => ['tag_o'],'plug:wb_master[1]' => ['tag_o']},'module_name' => 'lm32','parameters_order' => ['INTR_NUM','CFG_PL_MULTIPLY','CFG_PL_BARREL_SHIFT','CFG_SIGN_EXTEND','CFG_MC_DIVIDE'],'system_h' => '#include "lm32_system.h"inline void nop (void) {asm volatile ("nop");}','modules' => {'lm32' => {}},'ip_name' => 'lm32','plugs' => {'reset' => {'0' => {'name' => 'reset'},'type' => 'num','reset' => {},'1' => {'name' => 'reset_1'},'value' => 1},'clk' => {'0' => {'name' => 'clk'},'type' => 'num','clk' => {},'value' => 1},'enable' => {'enable' => {},'type' => 'num','0' => {'name' => 'enable'},'value' => 1},'wb_master' => {'1' => {'name' => 'dwb'},'value' => 2,'0' => {'name' => 'iwb'},'type' => 'num','wb_master' => {}}},'ports' => {'interrupt' => {'intfc_port' => 'int_i','type' => 'input','range' => '(32-1):0','intfc_name' => 'socket:interrupt_peripheral[array]'},'D_ACK_I' => {'intfc_port' => 'ack_i','type' => 'input','range' => '','intfc_name' => 'plug:wb_master[1]'},'D_RTY_I' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'rty_i','range' => '','type' => 'input'},'I_CTI_O' => {'intfc_name' => 'plug:wb_master[0]','type' => 'output','range' => '(3-1):0','intfc_port' => 'cti_o'},'I_DAT_O' => {'type' => 'output','range' => '(32-1):0','intfc_port' => 'dat_o','intfc_name' => 'plug:wb_master[0]'},'I_DAT_I' => {'type' => 'input','range' => '(32-1):0','intfc_port' => 'dat_i','intfc_name' => 'plug:wb_master[0]'},'D_ADR_O' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'adr_o','type' => 'output','range' => '(32-1):0'},'I_ACK_I' => {'intfc_port' => 'ack_i','type' => 'input','range' => '','intfc_name' => 'plug:wb_master[0]'},'I_BTE_O' => {'intfc_port' => 'bte_o','type' => 'output','range' => '(2-1):0','intfc_name' => 'plug:wb_master[0]'},'I_RTY_I' => {'intfc_name' => 'plug:wb_master[0]','range' => '','type' => 'input','intfc_port' => 'rty_i'},'clk_i' => {'type' => 'input','range' => '','intfc_port' => 'clk_i','intfc_name' => 'plug:clk[0]'},'D_CTI_O' => {'intfc_name' => 'plug:wb_master[1]','range' => '(3-1):0','type' => 'output','intfc_port' => 'cti_o'},'D_DAT_I' => {'intfc_name' => 'plug:wb_master[1]','type' => 'input','range' => '(32-1):0','intfc_port' => 'dat_i'},'D_WE_O' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'we_o','range' => '','type' => 'output'},'rst_i' => {'intfc_name' => 'plug:reset[0]','type' => 'input','range' => '','intfc_port' => 'reset_i'},'en_i' => {'type' => 'input','range' => '','intfc_port' => 'enable_i','intfc_name' => 'plug:enable[0]'},'D_BTE_O' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'bte_o','type' => 'output','range' => '(2-1):0'},'I_SEL_O' => {'intfc_name' => 'plug:wb_master[0]','range' => '(4-1):0','type' => 'output','intfc_port' => 'sel_o'},'D_DAT_O' => {'intfc_name' => 'plug:wb_master[1]','type' => 'output','range' => '(32-1):0','intfc_port' => 'dat_o'},'D_ERR_I' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'err_i','range' => '','type' => 'input'},'I_STB_O' => {'type' => 'output','range' => '','intfc_port' => 'stb_o','intfc_name' => 'plug:wb_master[0]'},'I_WE_O' => {'intfc_name' => 'plug:wb_master[0]','intfc_port' => 'we_o','range' => '','type' => 'output'},'I_ADR_O' => {'intfc_name' => 'plug:wb_master[0]','type' => 'output','range' => '(32-1):0','intfc_port' => 'adr_o'},'I_ERR_I' => {'intfc_name' => 'plug:wb_master[0]','type' => 'input','range' => '','intfc_port' => 'err_i'},'D_STB_O' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'stb_o','range' => '','type' => 'output'},'D_CYC_O' => {'intfc_name' => 'plug:wb_master[1]','intfc_port' => 'cyc_o','range' => '','type' => 'output'},'D_SEL_O' => {'range' => '(4-1):0','type' => 'output','intfc_port' => 'sel_o','intfc_name' => 'plug:wb_master[1]'},'I_CYC_O' => {'intfc_name' => 'plug:wb_master[0]','intfc_port' => 'cyc_o','type' => 'output','range' => ''}},'description' => 'The LatticeMico32 is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.for more information vist: http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx','ports_order' => ['clk_i','rst_i','en_i','interrupt','I_DAT_I','I_ACK_I','I_ERR_I','I_RTY_I','I_DAT_O','I_ADR_O','I_CYC_O','I_SEL_O','I_STB_O','I_WE_O','I_CTI_O','I_BTE_O','D_DAT_I','D_ACK_I','D_ERR_I','D_RTY_I','D_DAT_O','D_ADR_O','D_CYC_O','D_SEL_O','D_STB_O','D_WE_O','D_CTI_O','D_BTE_O'],'file_name' => '/home/alireza/Mywork/mpsoc/src_processor/lm32/verilog/src/lm32.v','version' => 2,'parameters' => {'CFG_MC_DIVIDE' => {'global_param' => 0,'content' => '"ENABLED","DISABLED"','info' => undef,'redefine_param' => 1,'default' => '"DISABLED"','type' => 'Fixed'},'INTR_NUM' => {'redefine_param' => 1,'info' => undef,'type' => 'Fixed','default' => '32','content' => '','global_param' => 0},'CFG_SIGN_EXTEND' => {'type' => 'Fixed','default' => '"ENABLED"','redefine_param' => 1,'info' => undef,'content' => '"ENABLED","DISABLED"','global_param' => 0},'CFG_PL_MULTIPLY' => {'content' => '"ENABLED","DISABLED"','global_param' => 0,'redefine_param' => 1,'info' => undef,'type' => 'Fixed','default' => '"ENABLED"'},'CFG_PL_BARREL_SHIFT' => {'content' => '"ENABLED","DISABLED"','global_param' => 0,'type' => 'Fixed','default' => '"ENABLED"','redefine_param' => 1,'info' => undef}},'gui_status' => {'status' => 'ideal','timeout' => 0}}, 'ip_gen' );
Go to most recent revision | Compare with Previous | Blame | View Log