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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [ip/] [RAM/] [single_port_ram.IP] - Rev 48
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######################################################################### File: single_port_ram.IP#### Copyright (C) 2014-2019 Alireza Monemi#### This file is part of ProNoC 1.9.1#### WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT## MAY CAUSE UNEXPECTED BEHAVIOR.################################################################################$ipgen = bless( {'sockets' => {'jtag_to_wb' => {'value' => 1,'0' => {'name' => 'jtag_to_wb'},'connection_num' => 'single connection','type' => 'num'}},'parameters_order' => ['Dw','Aw','WB_Aw','BYTE_WR_EN','FPGA_VENDOR','JTAG_CONNECT','JTAG_INDEX','CORE_NUM','TAGw','SELw','CTIw','BTEw','WB_Byte_Aw','BURST_MODE','MEM_CONTENT_FILE_NAME','INITIAL_EN','INIT_FILE_PATH','JDw','JAw','JSTATUSw','JINDEXw','J2WBw','WB2Jw','JTAG_CHAIN'],'description_pdf' => '/mpsoc/rtl/src_peripheral/ram/RAM.pdf','version' => 39,'parameters' => {'JTAG_INDEX' => {'default' => 'CORE_ID','info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).','type' => 'Entry','global_param' => 'Parameter','content' => '','redefine_param' => 1},'JAw' => {'content' => '','global_param' => 'Parameter','redefine_param' => 1,'default' => '32','type' => 'Fixed','info' => 'Parameter'},'INIT_FILE_PATH' => {'info' => undef,'type' => 'Fixed','default' => 'SW_LOC','redefine_param' => 1,'content' => '','global_param' => 'Localparam'},'FPGA_VENDOR' => {'global_param' => 'Localparam','content' => '"ALTERA","XILINX","GENERIC"','redefine_param' => 1,'default' => '"GENERIC"','info' => '','type' => 'Combo-box'},'Aw' => {'default' => '12','type' => 'Spin-button','info' => 'Memory address width','content' => '4,31,1','global_param' => 'Localparam','redefine_param' => 1},'CTIw' => {'redefine_param' => 1,'global_param' => 'Localparam','content' => '','info' => 'Parameter','type' => 'Fixed','default' => '3'},'JINDEXw' => {'redefine_param' => 1,'content' => '','global_param' => 'Parameter','type' => 'Fixed','info' => 'Parameter','default' => '8'},'INITIAL_EN' => {'default' => '"NO"','info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.','type' => 'Combo-box','global_param' => 'Localparam','content' => '"YES","NO"','redefine_param' => 1},'J2WBw' => {'info' => undef,'type' => 'Fixed','default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+1+JDw+JAw : 1','redefine_param' => 1,'content' => '','global_param' => 'Parameter'},'WB2Jw' => {'redefine_param' => 1,'content' => '','global_param' => 'Parameter','type' => 'Fixed','info' => undef,'default' => '(JTAG_CONNECT== "XILINX_JTAG_WB") ? 1+JSTATUSw+JINDEXw+1+JDw : 1'},'JDw' => {'type' => 'Fixed','info' => 'Parameter','default' => 'Dw','redefine_param' => 1,'global_param' => 'Parameter','content' => ''},'BTEw' => {'default' => '2','info' => 'Parameter','type' => 'Fixed','global_param' => 'Localparam','content' => '','redefine_param' => 1},'BURST_MODE' => {'info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ','type' => 'Combo-box','default' => '"ENABLED"','redefine_param' => 1,'content' => '"DISABLED","ENABLED"','global_param' => 'Localparam'},'WB_Aw' => {'info' => 'Wishbon bus reserved address with range. The reserved address will be 2 pow(WB_Aw) in words. This value should be larger or eqal than memory address width (Aw). ','type' => 'Spin-button','default' => '20','redefine_param' => 1,'global_param' => 'Localparam','content' => '4,31,1'},'Dw' => {'type' => 'Spin-button','info' => 'Memory data width in Bits.','default' => '32','redefine_param' => 1,'content' => '8,1024,1','global_param' => 'Parameter'},'JTAG_CHAIN' => {'info' => 'Only used for Virtex 4/5 devices. May be 1, 2, 3, or 4. It is the BSCANE2 JTAG tap number. The default Jtag tap numbers are:4: JTAG runtime memory programmers.3: UART1,2: reserved','type' => 'Combo-box','default' => '4','redefine_param' => 0,'content' => '1,2,3,4','global_param' => 'Parameter'},'BYTE_WR_EN' => {'redefine_param' => 1,'global_param' => 'Localparam','content' => '"YES","NO"','info' => 'Byte enable','type' => 'Combo-box','default' => '"YES"'},'SELw' => {'redefine_param' => 1,'content' => '','global_param' => 'Localparam','type' => 'Fixed','info' => 'Parameter','default' => 'Dw/8'},'WB_Byte_Aw' => {'global_param' => 'Don\'t include','content' => '','redefine_param' => 1,'default' => 'WB_Aw+2','info' => undef,'type' => 'Fixed'},'CORE_NUM' => {'global_param' => 'Localparam','content' => '','redefine_param' => 1,'default' => 'CORE_ID','info' => 'Parameter','type' => 'Fixed'},'TAGw' => {'type' => 'Fixed','info' => 'Parameter','default' => '3','redefine_param' => 1,'global_param' => 'Localparam','content' => ''},'JSTATUSw' => {'global_param' => 'Parameter','content' => '','redefine_param' => 1,'default' => '8','type' => 'Fixed','info' => 'Parameter'},'MEM_CONTENT_FILE_NAME' => {'redefine_param' => 1,'content' => '','global_param' => 'Localparam','type' => 'Entry','info' => 'MEM_FILE_NAME:The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.File Path:For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}file_type:bin: raw binary format . It will be used by ALTERA_JTAG_WB to change the memory content at runtime.memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ','default' => '"ram0"'},'JTAG_CONNECT' => {'default' => '"DISABLED"','type' => 'Combo-box','info' => 'JTAG_CONNECT:if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ','global_param' => 'Parameter','content' => '"DISABLED", "ALTERA_JTAG_WB" , "ALTERA_IMCE","XILINX_JTAG_WB"','redefine_param' => 1}},'module_name' => 'wb_single_port_ram','file_name' => 'mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v','plugs' => {'reset' => {'0' => {'name' => 'reset'},'value' => 1,'reset' => {},'type' => 'num'},'wb_slave' => {'type' => 'num','wb_slave' => {},'0' => {'addr' => '0x0000_0000 0x3fff_ffff RAM','name' => 'wb','width' => 'WB_Byte_Aw'},'value' => 1},'clk' => {'0' => {'name' => 'clk'},'value' => 1,'type' => 'num','clk' => {}}},'category' => 'RAM','ports' => {'sa_rty_o' => {'range' => '','type' => 'output','intfc_port' => 'rty_o','intfc_name' => 'plug:wb_slave[0]'},'sa_dat_o' => {'intfc_name' => 'plug:wb_slave[0]','type' => 'output','intfc_port' => 'dat_o','range' => 'Dw-1 : 0'},'sa_dat_i' => {'range' => 'Dw-1 : 0','type' => 'input','intfc_port' => 'dat_i','intfc_name' => 'plug:wb_slave[0]'},'clk' => {'intfc_name' => 'plug:clk[0]','intfc_port' => 'clk_i','type' => 'input','range' => ''},'jtag_to_wb' => {'intfc_name' => 'socket:jtag_to_wb[0]','range' => 'J2WBw-1 : 0','type' => 'input','intfc_port' => 'jwb_i'},'sa_ack_o' => {'type' => 'output','intfc_port' => 'ack_o','range' => '','intfc_name' => 'plug:wb_slave[0]'},'reset' => {'range' => '','intfc_port' => 'reset_i','type' => 'input','intfc_name' => 'plug:reset[0]'},'sa_err_o' => {'range' => '','intfc_port' => 'err_o','type' => 'output','intfc_name' => 'plug:wb_slave[0]'},'sa_stb_i' => {'range' => '','intfc_port' => 'stb_i','type' => 'input','intfc_name' => 'plug:wb_slave[0]'},'sa_tag_i' => {'range' => 'TAGw-1 : 0','type' => 'input','intfc_port' => 'tag_i','intfc_name' => 'plug:wb_slave[0]'},'sa_cyc_i' => {'range' => '','intfc_port' => 'cyc_i','type' => 'input','intfc_name' => 'plug:wb_slave[0]'},'sa_addr_i' => {'intfc_name' => 'plug:wb_slave[0]','range' => 'Aw-1 : 0','intfc_port' => 'adr_i','type' => 'input'},'sa_cti_i' => {'intfc_name' => 'plug:wb_slave[0]','range' => 'CTIw-1 : 0','type' => 'input','intfc_port' => 'cti_i'},'sa_sel_i' => {'range' => 'SELw-1 : 0','type' => 'input','intfc_port' => 'sel_i','intfc_name' => 'plug:wb_slave[0]'},'sa_we_i' => {'type' => 'input','intfc_port' => 'we_i','range' => '','intfc_name' => 'plug:wb_slave[0]'},'sa_bte_i' => {'intfc_name' => 'plug:wb_slave[0]','type' => 'input','intfc_port' => 'bte_i','range' => 'BTEw-1 : 0'},'wb_to_jtag' => {'type' => 'output','intfc_port' => 'jwb_o','range' => 'WB2Jw-1 : 0','intfc_name' => 'socket:jtag_to_wb[0]'}},'modules' => {'wb_single_port_ram' => {}},'ports_order' => ['clk','reset','jtag_to_wb','wb_to_jtag','sa_dat_i','sa_sel_i','sa_addr_i','sa_tag_i','sa_cti_i','sa_bte_i','sa_stb_i','sa_cyc_i','sa_we_i','sa_dat_o','sa_ack_o','sa_err_o','sa_rty_o'],'hdl_files' => ['/mpsoc/rtl/src_peripheral/ram/wb_single_port_ram.v','/mpsoc/rtl/src_peripheral/ram/generic_ram.v','/mpsoc/rtl/src_peripheral/ram/byte_enabled_generic_ram.sv','/mpsoc/rtl/src_peripheral/ram/wb_bram_ctrl.v'],'description' => 'Single port ram with wishbone bus interface.','unused' => undef,'ip_name' => 'single_port_ram','gui_status' => {'status' => 'ideal','timeout' => 0}}, 'ip_gen' );