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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [perl_gui/] [lib/] [soc/] [mor1k_tile.SOC] - Rev 42
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######################################################################### File: mor1k_tile.SOC#### Copyright (C) 2014-2016 Alireza Monemi#### This file is part of ProNoC 1.8.1#### WARNING: THIS IS AN AUTO-GENERATED FILE. CHANGES TO IT## MAY CAUSE UNEXPECTED BEHAIVOR.################################################################################$soc = bless( {'Unset-intfc' => {'bus-snoop_en_o' => 'NC','bus-snoop_adr_o' => 'NC','uart-RxD_ready_sim' => 'NC','uart-RxD_wr_sim' => 'NC','uart-RxD_din_sim' => 'NC'},'mor1kx0' => {'version' => 17},'wishbone_bus0' => {'version' => 1},'sim_uart0' => {'version' => 7},'single_port_ram0' => {'version' => 22},'global_param' => {'SW_LOC' => '/home/alireza/mywork/mpsoc_work/SOC/mor1k_tile/sw','CORE_ID' => 3},'clk_source0' => {'version' => 0},'gui_status' => {'status' => 'ideal','timeout' => 0},'ni_master0' => {'version' => 40},'timer0' => {'version' => 9},'instances' => {'wishbone_bus0' => {'parameters_order' => ['M','S','Dw','Aw','SELw','TAGw','CTIw','BTEw'],'category' => 'Bus','description_pdf' => undef,'module' => 'wishbone_bus','instance_name' => 'bus','parameters' => {'BTEw' => {'value' => '2 '},'Dw' => {'value' => '32'},'SELw' => {'value' => 'Dw/8'},'Aw' => {'value' => '32'},'CTIw' => {'value' => '3'},'TAGw' => {'value' => '3'},'S' => {'value' => '4'},'M' => {'value' => ' 4'}},'plugs' => {'reset' => {'type' => 'num','nums' => {'0' => {'name' => 'reset','connect_socket' => 'reset','connect_id' => 'clk_source0','connect_socket_num' => '0'}},'value' => 1,'connection_num' => undef},'clk' => {'nums' => {'0' => {'connect_id' => 'clk_source0','connect_socket_num' => '0','connect_socket' => 'clk','name' => 'clk'}},'type' => 'num','value' => 1,'connection_num' => undef}},'sockets' => {'wb_slave' => {'connection_num' => 'single connection','value' => 'S','nums' => {'0' => {'name' => 'wb_slave'}},'type' => 'param'},'wb_master' => {'nums' => {'0' => {'name' => 'wb_master'}},'type' => 'param','value' => 'M','connection_num' => 'single connection'},'wb_addr_map' => {'connection_num' => 'single connection','value' => 1,'nums' => {'0' => {'name' => 'wb_addr_map'}},'type' => 'num'},'snoop' => {'connection_num' => 'single connection','value' => 1,'type' => 'num','nums' => {'0' => {'name' => 'snoop'}}}},'module_name' => 'wishbone_bus'},'single_port_ram0' => {'parameters' => {'JTAG_CONNECT' => {'value' => '"DISABLED"'},'Aw' => {'value' => 14},'SELw' => {'value' => 'Dw/8'},'BURST_MODE' => {'value' => '"ENABLED"'},'INITIAL_EN' => {'value' => '"YES"'},'MEM_CONTENT_FILE_NAME' => {'value' => '"ram0"'},'BTEw' => {'value' => '2'},'Dw' => {'value' => '32'},'BYTE_WR_EN' => {'value' => '"YES"'},'INIT_FILE_PATH' => {'value' => 'SW_LOC'},'FPGA_VENDOR' => {'value' => '"ALTERA"'},'WB_Aw' => {'value' => 'Aw+2'},'JTAG_INDEX' => {'value' => 'CORE_ID'},'TAGw' => {'value' => '3'},'CTIw' => {'value' => '3'}},'plugs' => {'reset' => {'connection_num' => undef,'value' => 1,'type' => 'num','nums' => {'0' => {'connect_socket_num' => '0','connect_id' => 'clk_source0','name' => 'reset','connect_socket' => 'reset'}}},'wb_slave' => {'nums' => {'0' => {'connect_id' => 'wishbone_bus0','connect_socket_num' => '0','name' => 'wb','connect_socket' => 'wb_slave','base' => 0,'addr' => '0x0000_0000 0x3fff_ffff RAM','end' => 65535,'width' => 'WB_Aw'}},'type' => 'num','value' => 1,'connection_num' => undef},'clk' => {'value' => 1,'connection_num' => undef,'type' => 'num','nums' => {'0' => {'connect_socket_num' => '0','connect_id' => 'clk_source0','name' => 'clk','connect_socket' => 'clk'}}}},'module_name' => 'wb_single_port_ram','sockets' => {},'parameters_order' => ['Dw','Aw','BYTE_WR_EN','FPGA_VENDOR','JTAG_CONNECT','JTAG_INDEX','TAGw','SELw','CTIw','BTEw','WB_Aw','BURST_MODE','MEM_CONTENT_FILE_NAME','INITIAL_EN','INIT_FILE_PATH'],'description_pdf' => '/mpsoc/src_peripheral/ram/RAM.pdf','category' => 'RAM','module' => 'single_port_ram','instance_name' => 'ram'},'jtag_uart0' => {'plugs' => {'wb_slave' => {'connection_num' => undef,'value' => 1,'nums' => {'0' => {'connect_socket_num' => '1','connect_id' => 'wishbone_bus0','width' => 5,'end' => 2415919135,'addr' => '0x9000_0000 0x90ff_ffff UART16550 Controller','base' => 2415919104,'connect_socket' => 'wb_slave','name' => 'wb_slave'}},'type' => 'num'},'reset' => {'value' => 1,'connection_num' => undef,'nums' => {'0' => {'name' => 'reset','connect_socket' => 'reset','connect_socket_num' => '0','connect_id' => 'clk_source0'}},'type' => 'num'},'interrupt_peripheral' => {'type' => 'num','nums' => {'0' => {'connect_id' => 'NC','connect_socket_num' => undef,'name' => 'interrupt_peripheral','connect_socket' => undef}},'value' => 1,'connection_num' => undef},'clk' => {'connection_num' => undef,'value' => 1,'type' => 'num','nums' => {'0' => {'connect_socket' => 'clk','name' => 'clk','connect_socket_num' => '0','connect_id' => 'clk_source0'}}}},'parameters' => {'SIM_BUFFER_SIZE' => {'value' => 1000},'SIM_WAIT_COUNT' => {'value' => '1000'},'FPGA_VENDOR' => {'value' => ' "ALTERA"'}},'sockets' => {'RxD_sim' => {'connection_num' => 'single connection','value' => 1,'nums' => {'0' => {'name' => 'RxD_sim'}},'type' => 'num'}},'module_name' => 'jtag_uart_wb','category' => 'Communication','description_pdf' => undef,'parameters_order' => ['FPGA_VENDOR','SIM_BUFFER_SIZE','SIM_WAIT_COUNT'],'module' => 'jtag_uart','instance_name' => 'uart'},'clk_source0' => {'description_pdf' => undef,'category' => 'Source','parameters_order' => [],'module' => 'clk_source','instance_name' => 'ss','plugs' => {'clk' => {'value' => 1,'connection_num' => undef,'nums' => {'0' => {'name' => 'clk','connect_socket' => undef,'connect_socket_num' => undef,'connect_id' => 'IO'}},'type' => 'num'},'reset' => {'type' => 'num','nums' => {'0' => {'connect_socket_num' => undef,'connect_id' => 'IO','connect_socket' => undef,'name' => 'reset'}},'connection_num' => undef,'value' => 1}},'parameters' => {},'sockets' => {'clk' => {'nums' => {'0' => {'name' => 'clk'}},'type' => 'num','value' => 1,'connection_num' => 'multi connection'},'reset' => {'nums' => {'0' => {'name' => 'reset'}},'type' => 'num','value' => 1,'connection_num' => 'multi connection'}},'module_name' => 'clk_source'},'ni_master0' => {'sockets' => {'ni' => {'connection_num' => 'single connection','value' => 1,'nums' => {'0' => {'name' => 'ni'}},'type' => 'num'}},'module_name' => 'ni_master','parameters' => {'WEIGHTw' => {'value' => '4'},'COMBINATION_TYPE' => {'value' => '"COMB_NONSPEC"'},'MUX_TYPE' => {'value' => '"BINARY"'},'SELw' => {'value' => '4'},'ESCAP_VC_MASK' => {'value' => '2\'b01'},'MAX_TRANSACTION_WIDTH' => {'value' => '13'},'ROUTING_HDR_WIDTH' => {'value' => '8'},'NX' => {'value' => 2},'NY' => {'value' => ' 2'},'DST_ADR_HDR_WIDTH' => {'value' => '8'},'S_Aw' => {'value' => '8'},'B' => {'value' => '4'},'MAX_SBP_NUM ' => {'value' => 0},'M_Aw' => {'value' => '32'},'Yw' => {'value' => 'log2(NY)'},'DEBUG_EN' => {'value' => '1'},'SSA_EN' => {'value' => '"NO"'},'Xw' => {'value' => 'log2(NX)'},'ADD_PIPREG_AFTER_CROSSBAR' => {'value' => '1\'b0'},'CONGESTION_INDEX' => {'value' => 3},'TOPOLOGY' => {'value' => '"MESH"'},'Dw' => {'value' => '32'},'MAX_BURST_SIZE' => {'value' => '16'},'ROUTE_SUBFUNC' => {'value' => '"XY"'},'AVC_ATOMIC_EN' => {'value' => 0},'SWA_ARBITER_TYPE' => {'value' => '"RRA"'},'VC_REALLOCATION_TYPE' => {'value' => '"NONATOMIC"'},'SRC_ADR_HDR_WIDTH' => {'value' => '8'},'CLASS_HDR_WIDTH' => {'value' => '8'},'Fpay' => {'value' => '32'},'Fw' => {'value' => '2+V+Fpay'},'FIRST_ARBITER_EXT_P_EN' => {'value' => 1},'ROUTE_NAME' => {'value' => '"XY"'},'V' => {'value' => '2'},'CRC_EN' => {'value' => '"NO"'},'TAGw' => {'value' => '3'},'C' => {'value' => 2}},'plugs' => {'wb_slave' => {'connection_num' => undef,'value' => 1,'nums' => {'0' => {'connect_socket_num' => '3','connect_id' => 'wishbone_bus0','width' => 10,'end' => 3087008767,'base' => 3087007744,'addr' => '0xb800_0000 0xbfff_ffff custom devices','name' => 'wb_slave','connect_socket' => 'wb_slave'}},'type' => 'num'},'wb_master' => {'nums' => {'1' => {'connect_socket' => 'wb_master','name' => 'wb_receive','connect_id' => 'wishbone_bus0','connect_socket_num' => '1'},'0' => {'name' => 'wb_send','connect_socket' => 'wb_master','connect_id' => 'wishbone_bus0','connect_socket_num' => '0'}},'type' => 'num','value' => 2,'connection_num' => undef},'reset' => {'value' => 1,'connection_num' => undef,'nums' => {'0' => {'name' => 'reset','connect_socket' => 'reset','connect_socket_num' => '0','connect_id' => 'clk_source0'}},'type' => 'num'},'interrupt_peripheral' => {'type' => 'num','nums' => {'0' => {'name' => 'interrupt','connect_socket' => 'interrupt_peripheral','connect_socket_num' => '0','connect_id' => 'mor1kx0'}},'value' => 1,'connection_num' => undef},'clk' => {'connection_num' => undef,'value' => 1,'type' => 'num','nums' => {'0' => {'connect_socket' => 'clk','name' => 'clk','connect_socket_num' => '0','connect_id' => 'clk_source0'}}}},'module' => 'ni_master','instance_name' => 'ni','parameters_order' => ['CLASS_HDR_WIDTH','ROUTING_HDR_WIDTH','DST_ADR_HDR_WIDTH','SRC_ADR_HDR_WIDTH','TOPOLOGY','ROUTE_NAME','NX','NY','C','V','B','Fpay','MAX_TRANSACTION_WIDTH','MAX_BURST_SIZE','DEBUG_EN','Dw','S_Aw','M_Aw','TAGw','SELw','Xw','Yw','Fw','CRC_EN'],'category' => 'NoC','description_pdf' => '/mpsoc/src_peripheral/ni/NI.pdf'},'mor1kx0' => {'module' => 'mor1kx','instance_name' => 'cpu','parameters_order' => ['OPTION_OPERAND_WIDTH','IRQ_NUM','OPTION_DCACHE_SNOOP','FEATURE_INSTRUCTIONCACHE','FEATURE_DATACACHE','FEATURE_IMMU','FEATURE_DMMU'],'description_pdf' => undef,'category' => 'Processor','sockets' => {'interrupt_peripheral' => {'connection_num' => 'single connection','value' => 'IRQ_NUM','nums' => {'0' => {'name' => 'interrupt_peripheral'}},'type' => 'param'}},'module_name' => 'mor1k','parameters' => {'IRQ_NUM' => {'value' => '32'},'OPTION_OPERAND_WIDTH' => {'value' => '32'},'FEATURE_DMMU' => {'value' => '"ENABLED"'},'FEATURE_DATACACHE' => {'value' => '"ENABLED"'},'FEATURE_INSTRUCTIONCACHE' => {'value' => '"ENABLED"'},'FEATURE_IMMU' => {'value' => '"ENABLED"'},'OPTION_DCACHE_SNOOP' => {'value' => '"ENABLED"'}},'plugs' => {'wb_master' => {'connection_num' => undef,'value' => 2,'nums' => {'1' => {'connect_socket' => 'wb_master','name' => 'dwb','connect_socket_num' => '3','connect_id' => 'wishbone_bus0'},'0' => {'connect_id' => 'wishbone_bus0','connect_socket_num' => '2','connect_socket' => 'wb_master','name' => 'iwb'}},'type' => 'num'},'enable' => {'type' => 'num','nums' => {'0' => {'name' => 'enable','connect_socket' => undef,'connect_socket_num' => undef,'connect_id' => 'IO'}},'value' => 1,'connection_num' => undef},'snoop' => {'nums' => {'0' => {'name' => 'snoop','connect_socket' => 'snoop','connect_socket_num' => '0','connect_id' => 'wishbone_bus0'}},'type' => 'num','value' => 1,'connection_num' => undef},'reset' => {'connection_num' => undef,'value' => 1,'type' => 'num','nums' => {'0' => {'connect_id' => 'clk_source0','connect_socket_num' => '0','name' => 'reset','connect_socket' => 'reset'}}},'clk' => {'type' => 'num','nums' => {'0' => {'connect_socket' => 'clk','name' => 'clk','connect_id' => 'clk_source0','connect_socket_num' => '0'}},'value' => 1,'connection_num' => undef}}},'timer0' => {'instance_name' => 'timer','module' => 'timer','category' => 'Timer','description_pdf' => '/mpsoc/src_peripheral/timer/timer.pdf','parameters_order' => ['CNTw','Dw','Aw','TAGw','SELw','PRESCALER_WIDTH'],'sockets' => {},'module_name' => 'timer','plugs' => {'interrupt_peripheral' => {'type' => 'num','nums' => {'0' => {'name' => 'intrp','connect_socket' => 'interrupt_peripheral','connect_socket_num' => '1','connect_id' => 'mor1kx0'}},'value' => 1,'connection_num' => undef},'clk' => {'type' => 'num','nums' => {'0' => {'name' => 'clk','connect_socket' => 'clk','connect_id' => 'clk_source0','connect_socket_num' => '0'}},'value' => 1,'connection_num' => undef},'wb_slave' => {'nums' => {'0' => {'connect_socket' => 'wb_slave','name' => 'wb','end' => 2516582431,'width' => 5,'addr' => '0x9600_0000 0x96ff_ffff PWM/Timer/Counter Ctrl','base' => 2516582400,'connect_socket_num' => '2','connect_id' => 'wishbone_bus0'}},'type' => 'num','connection_num' => undef,'value' => 1},'reset' => {'connection_num' => undef,'value' => 1,'nums' => {'0' => {'connect_socket' => 'reset','name' => 'reset','connect_id' => 'clk_source0','connect_socket_num' => '0'}},'type' => 'num'}},'parameters' => {'Aw' => {'value' => '3'},'TAGw' => {'value' => '3'},'SELw' => {'value' => '4'},'Dw' => {'value' => '32'},'CNTw' => {'value' => '32 '},'PRESCALER_WIDTH' => {'value' => '8'}}}},'verilator' => {'libs' => {'Vtop' => 'mor1k_tile.v'}},'compile' => {'board' => 'DE10_Nano_VB2','modelsim_bin' => '/home/alireza/intelFPGA_lite/17.1/modelsim_ase/bin','compilers' => 'QuartusII,Verilator,Modelsim','type' => 'Verilator','quartus_bin' => '/home/alireza/intelFPGA_lite/17.1/quartus/bin'},'top_ip' => bless( {'ports' => {'ss_clk_in' => {'instance_name' => 'clk_source0','type' => 'input','range' => '','intfc_name' => 'plug:clk[0]','intfc_port' => 'clk_i'},'ni_flit_out_wr' => {'type' => 'output','intfc_name' => 'socket:ni[0]','range' => '','intfc_port' => 'flit_out_wr','instance_name' => 'ni_master0'},'ni_flit_out' => {'type' => 'output','range' => 'ni_Fw-1 : 0','intfc_name' => 'socket:ni[0]','intfc_port' => 'flit_out','instance_name' => 'ni_master0'},'ni_credit_out' => {'intfc_name' => 'socket:ni[0]','range' => 'ni_V-1 : 0','type' => 'output','intfc_port' => 'credit_out','instance_name' => 'ni_master0'},'ni_credit_in' => {'instance_name' => 'ni_master0','intfc_port' => 'credit_in','intfc_name' => 'socket:ni[0]','range' => 'ni_V-1 : 0','type' => 'input'},'ni_flit_in' => {'range' => 'ni_Fw-1 : 0','intfc_name' => 'socket:ni[0]','type' => 'input','intfc_port' => 'flit_in','instance_name' => 'ni_master0'},'ni_flit_in_wr' => {'intfc_port' => 'flit_in_wr','intfc_name' => 'socket:ni[0]','range' => '','type' => 'input','instance_name' => 'ni_master0'},'cpu_cpu_en' => {'intfc_port' => 'enable_i','range' => '','intfc_name' => 'plug:enable[0]','type' => 'input','instance_name' => 'mor1kx0'},'ni_current_y' => {'range' => 'ni_Yw-1 : 0','intfc_name' => 'socket:ni[0]','type' => 'input','intfc_port' => 'current_y','instance_name' => 'ni_master0'},'ni_current_x' => {'intfc_port' => 'current_x','type' => 'input','range' => 'ni_Xw-1 : 0','intfc_name' => 'socket:ni[0]','instance_name' => 'ni_master0'},'ss_reset_in' => {'intfc_port' => 'reset_i','type' => 'input','intfc_name' => 'plug:reset[0]','range' => '','instance_name' => 'clk_source0'}},'instance_ids' => {'mor1kx0' => {'module' => 'mor1kx','instance' => 'cpu','module_name' => 'mor1k','ports' => {'cpu_cpu_en' => {'intfc_port' => 'enable_i','type' => 'input','intfc_name' => 'plug:enable[0]','range' => ''}},'category' => 'Processor','parameters' => {'cpu_OPTION_OPERAND_WIDTH' => {'info' => 'Parameter','default' => '32','content' => '','global_param' => 'Parameter','redefine_param' => 1,'type' => 'Fixed'},'cpu_FEATURE_DMMU' => {'content' => '"NONE","ENABLED"','info' => '','default' => '"ENABLED"','redefine_param' => 1,'global_param' => 'Parameter','type' => 'Combo-box'},'cpu_FEATURE_IMMU' => {'default' => '"ENABLED"','info' => '','content' => '"NONE","ENABLED"','type' => 'Combo-box','global_param' => 'Parameter','redefine_param' => 1},'cpu_FEATURE_DATACACHE' => {'content' => '"NONE","ENABLED"','info' => '','default' => '"ENABLED"','redefine_param' => 1,'global_param' => 'Parameter','type' => 'Combo-box'},'cpu_OPTION_DCACHE_SNOOP' => {'content' => '"NONE","ENABLED"','info' => '','default' => '"ENABLED"','redefine_param' => 1,'global_param' => 'Parameter','type' => 'Combo-box'},'cpu_IRQ_NUM' => {'redefine_param' => 1,'global_param' => 'Parameter','type' => 'Fixed','content' => '','info' => undef,'default' => '32'},'cpu_FEATURE_INSTRUCTIONCACHE' => {'info' => '','default' => '"ENABLED"','content' => '"NONE","ENABLED"','type' => 'Combo-box','global_param' => 'Parameter','redefine_param' => 1}}},'timer0' => {'module' => 'timer','instance' => 'timer','localparam' => {'timer_SELw' => {'type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1,'default' => '4','info' => undef,'content' => ''},'timer_Aw' => {'default' => '3','info' => undef,'content' => '','type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1},'timer_TAGw' => {'global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed','info' => undef,'default' => '3','content' => ''},'timer_CNTw' => {'info' => undef,'default' => '32 ','content' => '','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed'},'timer_Dw' => {'global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed','default' => '32','info' => undef,'content' => ''}},'module_name' => 'timer','category' => 'Timer','parameters' => {'timer_PRESCALER_WIDTH' => {'redefine_param' => 1,'global_param' => 'Parameter','type' => 'Spin-button','content' => '1,32,1','default' => '8','info' => ' The prescaler timer width. The prescaler takes the basic timer clock frequency and divides it by some value before feeding it to the timer, according to how the prescaler register(s) are configured.'}}},'clk_source0' => {'instance' => 'ss','module' => 'clk_source','module_name' => 'clk_source','ports' => {'ss_clk_in' => {'intfc_port' => 'clk_i','intfc_name' => 'plug:clk[0]','range' => '','type' => 'input'},'ss_reset_in' => {'intfc_name' => 'plug:reset[0]','range' => '','type' => 'input','intfc_port' => 'reset_i'}},'category' => 'Source'},'ni_master0' => {'parameters' => {'ni_B' => {'content' => '','default' => '4','info' => 'Parameter','type' => 'Fixed','redefine_param' => 1,'global_param' => 'Parameter'},'ni_NX' => {'type' => 'Fixed','redefine_param' => 1,'global_param' => 'Parameter','content' => '','info' => 'Parameter','default' => 2},'ni_NY' => {'content' => '','default' => ' 2','info' => 'Parameter','redefine_param' => 1,'global_param' => 'Parameter','type' => 'Fixed'},'ni_TOPOLOGY' => {'content' => '','default' => '"MESH"','info' => 'Parameter','redefine_param' => 1,'global_param' => 'Parameter','type' => 'Fixed'},'ni_V' => {'content' => '','default' => '2','info' => 'Parameter','type' => 'Fixed','redefine_param' => 1,'global_param' => 'Parameter'},'ni_Fpay' => {'default' => '32','info' => 'Parameter','content' => '','type' => 'Fixed','global_param' => 'Parameter','redefine_param' => 1},'ni_C' => {'type' => 'Fixed','global_param' => 'Parameter','redefine_param' => 1,'default' => 2,'info' => 'Parameter','content' => ''},'ni_ROUTE_NAME' => {'info' => 'Parameter','default' => '"XY"','content' => '','global_param' => 'Parameter','redefine_param' => 1,'type' => 'Fixed'},'ni_DEBUG_EN' => {'default' => '1','info' => 'Parameter','content' => '','type' => 'Fixed','global_param' => 'Parameter','redefine_param' => 1}},'category' => 'NoC','ports' => {'ni_flit_out_wr' => {'range' => '','intfc_name' => 'socket:ni[0]','type' => 'output','intfc_port' => 'flit_out_wr'},'ni_credit_in' => {'intfc_port' => 'credit_in','range' => 'ni_V-1 : 0','intfc_name' => 'socket:ni[0]','type' => 'input'},'ni_credit_out' => {'intfc_port' => 'credit_out','type' => 'output','intfc_name' => 'socket:ni[0]','range' => 'ni_V-1 : 0'},'ni_flit_out' => {'intfc_port' => 'flit_out','type' => 'output','range' => 'ni_Fw-1 : 0','intfc_name' => 'socket:ni[0]'},'ni_flit_in' => {'intfc_port' => 'flit_in','intfc_name' => 'socket:ni[0]','range' => 'ni_Fw-1 : 0','type' => 'input'},'ni_flit_in_wr' => {'range' => '','intfc_name' => 'socket:ni[0]','type' => 'input','intfc_port' => 'flit_in_wr'},'ni_current_y' => {'intfc_port' => 'current_y','type' => 'input','range' => 'ni_Yw-1 : 0','intfc_name' => 'socket:ni[0]'},'ni_current_x' => {'range' => 'ni_Xw-1 : 0','intfc_name' => 'socket:ni[0]','type' => 'input','intfc_port' => 'current_x'}},'module_name' => 'ni_master','localparam' => {'ni_DST_ADR_HDR_WIDTH' => {'default' => '8','info' => 'Parameter','content' => '','type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1},'ni_CRC_EN' => {'type' => 'Combo-box','global_param' => 'Localparam','redefine_param' => 1,'default' => '"NO"','info' => 'The parameter can be selected as "YES" or "NO".If CRC is enabled, then two CRC32 generator modules will be added to the NI. One CRC generator for calculating CRC of sending packets and another for receiving packets. The CRC32 value of each packet is send via tail flit and at destination NI, is will be compared with received packet generated CRC32. The matching results can be used for error-detection and can be read via NI slave interface. ','content' => '"YES","NO"'},'ni_S_Aw' => {'type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1,'default' => '8','info' => 'Parameter','content' => ''},'ni_M_Aw' => {'type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1,'default' => '32','info' => 'Parameter','content' => 'Dw'},'ni_SRC_ADR_HDR_WIDTH' => {'content' => '','info' => 'Parameter','default' => '8','redefine_param' => 1,'global_param' => 'Localparam','type' => 'Fixed'},'ni_Fw' => {'type' => 'Fixed','redefine_param' => 0,'global_param' => 'Localparam','content' => '','default' => '2+ni_V+ni_Fpay','info' => undef},'ni_Xw' => {'global_param' => 'Localparam','redefine_param' => 0,'type' => 'Fixed','default' => 'log2(ni_NX)','info' => undef,'content' => ''},'ni_TAGw' => {'type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam','content' => '','default' => '3','info' => 'Parameter'},'ni_SELw' => {'content' => '','info' => 'Parameter','default' => '4','type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam'},'ni_ROUTING_HDR_WIDTH' => {'type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 1,'info' => 'Parameter','default' => '8','content' => ''},'ni_MAX_TRANSACTION_WIDTH' => {'default' => '13','info' => 'maximum packet size width in words.The maximum data that can be sent via one packet will be 2 power of MAX_DMA_TRANSACTION_WIDTH in words.','content' => '4,32,1','type' => 'Spin-button','global_param' => 'Localparam','redefine_param' => 1},'ni_MAX_BURST_SIZE' => {'type' => 'Combo-box','redefine_param' => 1,'global_param' => 'Localparam','content' => '2,4,8,16,32,64,128,256,512,1024,2048','info' => 'Maximum burst size in words.The NI releases the wishbone bus each time one burst is completed or when the VC\'s internal FIFO becomes full. The bus will be released for one clock cycle. Then in case, there are other active VCs, another active VC will get access to the bus using round robin arbiter. This process will be continued until all of the desired data is transferred. ','default' => '16'},'ni_Dw' => {'content' => '32,256,8','info' => 'wishbone_bus data width in bits.','default' => '32','redefine_param' => 1,'global_param' => 'Localparam','type' => 'Spin-button'},'ni_CLASS_HDR_WIDTH' => {'default' => '8','info' => 'Parameter','content' => '','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed'},'ni_Yw' => {'default' => 'log2(ni_NY)','info' => undef,'content' => '','type' => 'Fixed','global_param' => 'Localparam','redefine_param' => 0}},'module' => 'ni_master','instance' => 'ni'},'jtag_uart0' => {'category' => 'Communication','module_name' => 'jtag_uart_wb','localparam' => {'uart_FPGA_VENDOR' => {'default' => ' "ALTERA"','info' => 'FPGA VENDOR name. Only Altera FPGA is supported. Currently the Generic serial port is not supported. ','content' => ' "ALTERA"','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Combo-box'},'uart_SIM_BUFFER_SIZE' => {'info' => 'Internal buffer size.This parameter is valid only in simulation.If internal buffer overflows, the buffer content are displayed on simulator terminal.','default' => 1000,'content' => '10,10000,1','type' => 'Spin-button','global_param' => 'Localparam','redefine_param' => 1},'uart_SIM_WAIT_COUNT' => {'content' => '2,100000,1','info' => 'This parameter is valid only in simulation.If internal buffer has a data, the internal timer incremented by one in each clock cycle. If the timer reaches the WAIT_COUNT value, it writes the buffer value on the simulator terminal.','default' => '1000','type' => 'Spin-button','redefine_param' => 1,'global_param' => 'Localparam'}},'module' => 'jtag_uart','instance' => 'uart'},'wishbone_bus0' => {'module' => 'wishbone_bus','instance' => 'bus','localparam' => {'bus_CTIw' => {'default' => '3','info' => undef,'content' => '','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed'},'bus_M' => {'redefine_param' => 1,'global_param' => 'Localparam','type' => 'Spin-button','content' => '1,256,1','default' => ' 4','info' => 'Number of wishbone master interface'},'bus_BTEw' => {'content' => '','default' => '2 ','info' => undef,'redefine_param' => 1,'global_param' => 'Localparam','type' => 'Fixed'},'bus_Aw' => {'default' => '32','info' => 'The wishbone Bus address width','content' => '4,128,1','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Spin-button'},'bus_TAGw' => {'content' => '','info' => undef,'default' => '3','type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam'},'bus_S' => {'content' => '1,256,1','default' => '4','info' => 'Number of wishbone slave interface','redefine_param' => 1,'global_param' => 'Localparam','type' => 'Spin-button'},'bus_Dw' => {'global_param' => 'Localparam','redefine_param' => 1,'type' => 'Spin-button','info' => 'The wishbone Bus data width in bits.','default' => '32','content' => '8,512,8'},'bus_SELw' => {'content' => '','default' => 'bus_Dw/8','info' => undef,'redefine_param' => 1,'global_param' => 'Localparam','type' => 'Fixed'}},'module_name' => 'wishbone_bus','category' => 'Bus'},'single_port_ram0' => {'category' => 'RAM','parameters' => {'ram_Dw' => {'global_param' => 'Parameter','redefine_param' => 1,'type' => 'Spin-button','default' => '32','info' => 'Memory data width in Bits.','content' => '8,1024,1'},'ram_Aw' => {'default' => 14,'info' => 'Memory address width','content' => '4,31,1','type' => 'Spin-button','global_param' => 'Parameter','redefine_param' => 1}},'module_name' => 'wb_single_port_ram','localparam' => {'ram_SELw' => {'content' => '','default' => 'ram_Dw/8','info' => 'Parameter','type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam'},'ram_FPGA_VENDOR' => {'type' => 'Combo-box','redefine_param' => 1,'global_param' => 'Localparam','content' => '"ALTERA","GENERIC"','info' => '','default' => '"ALTERA"'},'ram_BURST_MODE' => {'content' => '"DISABLED","ENABLED"','default' => '"ENABLED"','info' => 'Enable the Wishbone bus Incrementing burst mode data transfer. Support Linear burst and 4,8,16-beat wrap burst types. ','type' => 'Combo-box','redefine_param' => 1,'global_param' => 'Localparam'},'ram_MEM_CONTENT_FILE_NAME' => {'info' => 'MEM_FILE_NAME:The memory file name (without file type extension ) that is used for writting the memory content either at run time or at initialization time.File Path:For bus-based SoC the file path is {ProNoC_work}/SOC/{soc_name}/sw/RAM/{file_type}/{MEM_FILE_NAME}.For NoC-based MPSoC the file path is {ProNoC_work}/MPSOC/{mpsoc_name}/sw/tile{tile_num}/RAM/{file_type}/{MEM_FILE_NAME}file_type:bin: raw binary format . It will be used by JTAG_WB to change the memory content at runtime.memh: hexadecimal-string format . It will be used for initialing the Generic RAM using $readmemh command.mif: memory initialization file format. This file can be used to initialize Altera FPGA memory. Also if the JTAG_CONECT is selected as ALTERA_IEMC it can be used for changing memory content at run time . ','default' => '"ram0"','content' => '','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Entry'},'ram_INITIAL_EN' => {'content' => '"YES","NO"','default' => '"YES"','info' => 'If selected as "ENABLED", the memory content will be initialized at compilation time using MEM_CONTENT_FILE_NAME.','type' => 'Combo-box','redefine_param' => 1,'global_param' => 'Localparam'},'ram_BTEw' => {'type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam','content' => '','default' => '2','info' => 'Parameter'},'ram_JTAG_CONNECT' => {'global_param' => 'Localparam','redefine_param' => 1,'type' => 'Combo-box','default' => '"DISABLED"','info' => 'JTAG_CONNECT:if it is not disabled then the actual memory is implemented as a dual port RAM with the second port is connected either to In-System Memory Content Editor or Jtag_to_wb. This allows that the memory content can be read/written using JTAG. ','content' => '"DISABLED", "JTAG_WB" , "ALTERA_IMCE"'},'ram_JTAG_INDEX' => {'type' => 'Entry','global_param' => 'Localparam','redefine_param' => 1,'info' => ' A unique index number which will be used for accessing to the memory content using JTAG cable.The default value is the processing tile id (CORE_ID) . You can also inter a unique number for each individula memory.In case you have \'n\' memory in each processing core you can define their index as "n*CORE_ID+1 , n*CORE_ID+2 ...n*CORE_ID+n-1).You also can disabled JTAG access here and connect one jtag to wb interface (jtag_wb) to the wishbone bus. Using single jtag index number, a jtag_wb module can read/wr any IP that is connected to wishbone bus slave port (including all memory units).','default' => 'CORE_ID','content' => ''},'ram_INIT_FILE_PATH' => {'info' => undef,'default' => 'SW_LOC','content' => '','global_param' => 'Localparam','redefine_param' => 1,'type' => 'Fixed'},'ram_BYTE_WR_EN' => {'redefine_param' => 1,'global_param' => 'Localparam','type' => 'Combo-box','content' => '"YES","NO"','info' => 'Byte enable','default' => '"YES"'},'ram_TAGw' => {'type' => 'Fixed','redefine_param' => 1,'global_param' => 'Localparam','content' => '','info' => 'Parameter','default' => '3'},'ram_CTIw' => {'content' => '','default' => '3','info' => 'Parameter','redefine_param' => 1,'global_param' => 'Localparam','type' => 'Fixed'}},'instance' => 'ram','module' => 'single_port_ram'}},'interface' => {'socket:ni[0]' => {'ports' => {'ni_current_x' => {'instance_name' => 'ni_master0','range' => 'ni_Xw-1 : 0','type' => 'input','intfc_port' => 'current_x'},'ni_flit_in_wr' => {'type' => 'input','range' => '','intfc_port' => 'flit_in_wr','instance_name' => 'ni_master0'},'ni_current_y' => {'intfc_port' => 'current_y','range' => 'ni_Yw-1 : 0','type' => 'input','instance_name' => 'ni_master0'},'ni_flit_in' => {'instance_name' => 'ni_master0','intfc_port' => 'flit_in','range' => 'ni_Fw-1 : 0','type' => 'input'},'ni_flit_out_wr' => {'range' => '','type' => 'output','intfc_port' => 'flit_out_wr','instance_name' => 'ni_master0'},'ni_credit_in' => {'instance_name' => 'ni_master0','range' => 'ni_V-1 : 0','type' => 'input','intfc_port' => 'credit_in'},'ni_credit_out' => {'instance_name' => 'ni_master0','intfc_port' => 'credit_out','range' => 'ni_V-1 : 0','type' => 'output'},'ni_flit_out' => {'instance_name' => 'ni_master0','type' => 'output','range' => 'ni_Fw-1 : 0','intfc_port' => 'flit_out'}}},'plug:enable[0]' => {'ports' => {'cpu_cpu_en' => {'instance_name' => 'mor1kx0','intfc_port' => 'enable_i','type' => 'input','range' => ''}}},'plug:reset[0]' => {'ports' => {'ss_reset_in' => {'range' => '','type' => 'input','intfc_port' => 'reset_i','instance_name' => 'clk_source0'}}},'plug:clk[0]' => {'ports' => {'ss_clk_in' => {'intfc_port' => 'clk_i','type' => 'input','range' => '','instance_name' => 'clk_source0'}}}}}, 'ip_gen' ),'tile_diagram' => {'show_unused' => 1,'show_clk' => 1,'show_reset' => 1},'soc_name' => 'mor1k_tile','instance_order' => ['single_port_ram0','clk_source0','jtag_uart0','timer0','ni_master0','wishbone_bus0','mor1kx0'],'compile_pin_pos' => {},'jtag_uart0' => {'version' => 14},'hdl_files' => undef,'parameters_order' => {'Unset-intfc' => ['uart-RxD_din_sim','uart-RxD_ready_sim','uart-RxD_wr_sim','bus-snoop_adr_o','bus-snoop_en_o']},'compile_assign_type' => {'ss_clk_in' => 'Direct','ni_credit_in' => 'Direct','ni_flit_in' => 'Direct','ni_flit_in_wr' => 'Direct','cpu_cpu_en' => 'Direct','ni_current_y' => 'Direct','ni_current_x' => 'Direct','ss_reset_in' => 'Direct'},'dma0' => {'version' => 4},'modules' => {}}, 'soc' );
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