URL
https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk
Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc
[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [script/] [server/] [kc07/] [hardware] - Rev 48
Compare with Previous | Blame | View Log
Report Instance Areas:+------+-------------------------------------------------------------+--------------------------------------------------+------+| |Instance |Module |Cells |+------+-------------------------------------------------------------+--------------------------------------------------+------+|1 |top | | 37643||2 | uut |kc07_mesh_top | 37632||3 | jwb_3 |xilinx_jtag_wb__parameterized0 | 194||4 | \block[0].ack_latch |wb_to_jtag_latch_535 | 4||5 | \block[1].ack_latch |wb_to_jtag_latch_536 | 4||6 | \block[2].ack_latch |wb_to_jtag_latch_537 | 4||7 | \block[3].ack_latch |wb_to_jtag_latch_538 | 4||8 | mem_ctrl |xilinx_jtag_mem_ctrl__parameterized0 | 177||9 | vjtag_ctrl_inst |xilinx_jtag_ctrl__parameterized0 | 157||10 | vjtag_inst |xilinx_jtag_bscan__parameterized0 | 47||11 | jwb_4 |xilinx_jtag_wb | 319||12 | \block[0].ack_latch |wb_to_jtag_latch | 4||13 | \block[1].ack_latch |wb_to_jtag_latch_532 | 4||14 | \block[2].ack_latch |wb_to_jtag_latch_533 | 4||15 | \block[3].ack_latch |wb_to_jtag_latch_534 | 4||16 | mem_ctrl |xilinx_jtag_mem_ctrl | 297||17 | vjtag_ctrl_inst |xilinx_jtag_ctrl | 247||18 | vjtag_inst |xilinx_jtag_bscan | 52||19 | pll |xilinx_pll2_base | 1||20 | the_kc07_mesh |kc07_mesh | 37117||21 | the_mor1k_tile_0 |mor1k_tile | 8166||22 | bus |wishbone_bus_471 | 471||23 | arbiter |bus_arbiter__parameterized0_529 | 471||24 | the_combinational_arbiter |arbiter__parameterized0_530 | 2||25 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_531 | 2||26 | cpu |mor1k_472 | 6060||27 | mor1kx0 |mor1kx_495 | 5890||28 | mor1kx_cpu |mor1kx_cpu_496 | 5890||29 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_497 | 5888||30 | mor1kx_branch_prediction |mor1kx_branch_prediction_498 | 2||31 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_499 | 827||32 | \pic.mor1kx_pic |mor1kx_pic_527 | 144||33 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_528 | 118||34 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_500 | 638||35 | mor1kx_execute_alu |mor1kx_execute_alu_501 | 297||36 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_502 | 984||37 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_503 | 908||38 | \icache_gen.mor1kx_icache |mor1kx_icache_520 | 294||39 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_524 | 130||40 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_525 | 15||41 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_526 | 42||42 | \immu_gen.mor1kx_immu |mor1kx_immu_521 | 236||43 | itlb_match_regs |mor1kx_true_dpram_sclk_522 | 166||44 | itlb_translate_regs |mor1kx_true_dpram_sclk_523 | 25||45 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_504 | 1387||46 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_510 | 800||47 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_516 | 375||48 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_517 | 191||49 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_518 | 72||50 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_519 | 23||51 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_511 | 240||52 | dtlb_match_regs |mor1kx_true_dpram_sclk_514 | 60||53 | dtlb_translate_regs |mor1kx_true_dpram_sclk_515 | 175||54 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_512 | 162||55 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_513 | 121||56 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_505 | 734||57 | rfa |mor1kx_simple_dpram_sclk__parameterized5_507 | 33||58 | rfb |mor1kx_simple_dpram_sclk__parameterized5_508 | 33||59 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_509 | 1||60 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_506 | 111||61 | led |gpo_473 | 2||62 | ni |ni_master_474 | 1019||63 | \multi_channel.receive_arbiter |bus_arbiter_480 | 11||64 | the_combinational_arbiter |arbiter_493 | 2||65 | \w4.one_hot_arb |my_one_hot_arbiter_494 | 2||66 | \multi_channel.send_arbiter |bus_arbiter_481 | 10||67 | the_combinational_arbiter |arbiter_491 | 2||68 | \w4.one_hot_arb |my_one_hot_arbiter_492 | 2||69 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_482 | 11||70 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_483 | 14||71 | the_ififo |flit_buffer_484 | 81||72 | \pow2.the_queue |fifo_ram_490 | 49||73 | the_ovc_status |ovc_status_485 | 15||74 | \vc_[0].vc_dma |ni_vc_dma_486 | 215||75 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_487 | 191||76 | \vc_[1].vc_dma |ni_vc_dma_488 | 213||77 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_489 | 224||78 | ram |wb_single_port_ram | 296||79 | ctrl |wb_bram_ctrl_478 | 226||80 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_479 | 226||81 | ram_top |single_port_ram_top | 70||82 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram | 64||83 | xpm_memory_base_inst |xpm_memory_base | 64||84 | timer |timer_475 | 187||85 | uart |pronoc_jtag_uart | 131||86 | uart_hw |pronoc_jtag_uart_hw | 131||87 | jtag_to_wb_fifo |uart_fifo_476 | 57||88 | wb_to_jtag_fifo |uart_fifo_477 | 66||89 | the_mor1k_tile_1 |mor1k_tile__parameterized0 | 8154||90 | bus |wishbone_bus_410 | 465||91 | arbiter |bus_arbiter__parameterized0_468 | 465||92 | the_combinational_arbiter |arbiter__parameterized0_469 | 2||93 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_470 | 2||94 | cpu |mor1k_411 | 6061||95 | mor1kx0 |mor1kx_434 | 5891||96 | mor1kx_cpu |mor1kx_cpu_435 | 5891||97 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_436 | 5889||98 | mor1kx_branch_prediction |mor1kx_branch_prediction_437 | 2||99 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_438 | 847||100 | \pic.mor1kx_pic |mor1kx_pic_466 | 145||101 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_467 | 118||102 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_439 | 638||103 | mor1kx_execute_alu |mor1kx_execute_alu_440 | 297||104 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_441 | 984||105 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_442 | 889||106 | \icache_gen.mor1kx_icache |mor1kx_icache_459 | 294||107 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_463 | 130||108 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_464 | 15||109 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_465 | 42||110 | \immu_gen.mor1kx_immu |mor1kx_immu_460 | 217||111 | itlb_match_regs |mor1kx_true_dpram_sclk_461 | 148||112 | itlb_translate_regs |mor1kx_true_dpram_sclk_462 | 25||113 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_443 | 1387||114 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_449 | 800||115 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_455 | 375||116 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_456 | 191||117 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_457 | 72||118 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_458 | 23||119 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_450 | 240||120 | dtlb_match_regs |mor1kx_true_dpram_sclk_453 | 60||121 | dtlb_translate_regs |mor1kx_true_dpram_sclk_454 | 175||122 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_451 | 162||123 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_452 | 121||124 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_444 | 734||125 | rfa |mor1kx_simple_dpram_sclk__parameterized5_446 | 33||126 | rfb |mor1kx_simple_dpram_sclk__parameterized5_447 | 33||127 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_448 | 1||128 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_445 | 111||129 | led |gpo_412 | 2||130 | ni |ni_master_413 | 1017||131 | \multi_channel.receive_arbiter |bus_arbiter_419 | 11||132 | the_combinational_arbiter |arbiter_432 | 2||133 | \w4.one_hot_arb |my_one_hot_arbiter_433 | 2||134 | \multi_channel.send_arbiter |bus_arbiter_420 | 10||135 | the_combinational_arbiter |arbiter_430 | 2||136 | \w4.one_hot_arb |my_one_hot_arbiter_431 | 2||137 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_421 | 11||138 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_422 | 13||139 | the_ififo |flit_buffer_423 | 81||140 | \pow2.the_queue |fifo_ram_429 | 49||141 | the_ovc_status |ovc_status_424 | 15||142 | \vc_[0].vc_dma |ni_vc_dma_425 | 215||143 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_426 | 192||144 | \vc_[1].vc_dma |ni_vc_dma_427 | 213||145 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_428 | 222||146 | ram |wb_single_port_ram__parameterized0 | 291||147 | ctrl |wb_bram_ctrl_417 | 226||148 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_418 | 226||149 | ram_top |single_port_ram_top__parameterized0 | 65||150 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized0 | 64||151 | xpm_memory_base_inst |xpm_memory_base__parameterized0 | 64||152 | timer |timer_414 | 187||153 | uart |pronoc_jtag_uart__parameterized0 | 131||154 | uart_hw |pronoc_jtag_uart_hw__parameterized0 | 131||155 | jtag_to_wb_fifo |uart_fifo_415 | 57||156 | wb_to_jtag_fifo |uart_fifo_416 | 66||157 | the_mor1k_tile_2 |mor1k_tile__parameterized1 | 8205||158 | bus |wishbone_bus_349 | 561||159 | arbiter |bus_arbiter__parameterized0_407 | 561||160 | the_combinational_arbiter |arbiter__parameterized0_408 | 12||161 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_409 | 12||162 | cpu |mor1k_350 | 6037||163 | mor1kx0 |mor1kx_373 | 5867||164 | mor1kx_cpu |mor1kx_cpu_374 | 5867||165 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino_375 | 5865||166 | mor1kx_branch_prediction |mor1kx_branch_prediction_376 | 2||167 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino_377 | 827||168 | \pic.mor1kx_pic |mor1kx_pic_405 | 144||169 | \tt.mor1kx_ticktimer |mor1kx_ticktimer_406 | 118||170 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino_378 | 638||171 | mor1kx_execute_alu |mor1kx_execute_alu_379 | 297||172 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino_380 | 984||173 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino_381 | 910||174 | \icache_gen.mor1kx_icache |mor1kx_icache_398 | 296||175 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0_402 | 130||176 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk_403 | 15||177 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_404 | 42||178 | \immu_gen.mor1kx_immu |mor1kx_immu_399 | 236||179 | itlb_match_regs |mor1kx_true_dpram_sclk_400 | 166||180 | itlb_translate_regs |mor1kx_true_dpram_sclk_401 | 25||181 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino_382 | 1362||182 | \dcache_gen.mor1kx_dcache |mor1kx_dcache_388 | 802||183 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3_394 | 375||184 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4_395 | 191||185 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_396 | 72||186 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_397 | 23||187 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu_389 | 241||188 | dtlb_match_regs |mor1kx_true_dpram_sclk_392 | 60||189 | dtlb_translate_regs |mor1kx_true_dpram_sclk_393 | 176||190 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer_390 | 162||191 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1_391 | 121||192 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino_383 | 734||193 | rfa |mor1kx_simple_dpram_sclk__parameterized5_385 | 33||194 | rfb |mor1kx_simple_dpram_sclk__parameterized5_386 | 33||195 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_387 | 1||196 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino_384 | 111||197 | led |gpo_351 | 2||198 | ni |ni_master_352 | 1023||199 | \multi_channel.receive_arbiter |bus_arbiter_358 | 11||200 | the_combinational_arbiter |arbiter_371 | 2||201 | \w4.one_hot_arb |my_one_hot_arbiter_372 | 2||202 | \multi_channel.send_arbiter |bus_arbiter_359 | 39||203 | the_combinational_arbiter |arbiter_369 | 2||204 | \w4.one_hot_arb |my_one_hot_arbiter_370 | 2||205 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1_360 | 13||206 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_361 | 15||207 | the_ififo |flit_buffer_362 | 72||208 | \pow2.the_queue |fifo_ram_368 | 42||209 | the_ovc_status |ovc_status_363 | 16||210 | \vc_[0].vc_dma |ni_vc_dma_364 | 224||211 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs_365 | 193||212 | \vc_[1].vc_dma |ni_vc_dma_366 | 217||213 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_367 | 191||214 | ram |wb_single_port_ram__parameterized1 | 291||215 | ctrl |wb_bram_ctrl_356 | 226||216 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl_357 | 226||217 | ram_top |single_port_ram_top__parameterized1 | 65||218 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized1 | 64||219 | xpm_memory_base_inst |xpm_memory_base__parameterized1 | 64||220 | timer |timer_353 | 153||221 | uart |pronoc_jtag_uart__parameterized1 | 138||222 | uart_hw |pronoc_jtag_uart_hw__parameterized1 | 138||223 | jtag_to_wb_fifo |uart_fifo_354 | 70||224 | wb_to_jtag_fifo |uart_fifo_355 | 57||225 | the_mor1k_tile_3 |mor1k_tile__parameterized2 | 8183||226 | bus |wishbone_bus | 474||227 | arbiter |bus_arbiter__parameterized0 | 474||228 | the_combinational_arbiter |arbiter__parameterized0_347 | 2||229 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_348 | 2||230 | cpu |mor1k | 6061||231 | mor1kx0 |mor1kx | 5889||232 | mor1kx_cpu |mor1kx_cpu | 5889||233 | \cappuccino.mor1kx_cpu |mor1kx_cpu_cappuccino | 5887||234 | mor1kx_branch_prediction |mor1kx_branch_prediction | 2||235 | mor1kx_ctrl_cappuccino |mor1kx_ctrl_cappuccino | 827||236 | \pic.mor1kx_pic |mor1kx_pic | 144||237 | \tt.mor1kx_ticktimer |mor1kx_ticktimer | 118||238 | mor1kx_decode_execute_cappuccino |mor1kx_decode_execute_cappuccino | 638||239 | mor1kx_execute_alu |mor1kx_execute_alu | 297||240 | mor1kx_execute_ctrl_cappuccino |mor1kx_execute_ctrl_cappuccino | 984||241 | mor1kx_fetch_cappuccino |mor1kx_fetch_cappuccino | 908||242 | \icache_gen.mor1kx_icache |mor1kx_icache | 294||243 | tag_ram |mor1kx_simple_dpram_sclk__parameterized0 | 130||244 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk | 15||245 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk_346 | 42||246 | \immu_gen.mor1kx_immu |mor1kx_immu | 236||247 | itlb_match_regs |mor1kx_true_dpram_sclk_344 | 166||248 | itlb_translate_regs |mor1kx_true_dpram_sclk_345 | 25||249 | mor1kx_lsu_cappuccino |mor1kx_lsu_cappuccino | 1386||250 | \dcache_gen.mor1kx_dcache |mor1kx_dcache | 800||251 | snoop_tag_ram |mor1kx_simple_dpram_sclk__parameterized3 | 375||252 | tag_ram |mor1kx_simple_dpram_sclk__parameterized4 | 191||253 | \way_memories[0].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2 | 72||254 | \way_memories[1].way_data_ram |mor1kx_simple_dpram_sclk__parameterized2_343 | 23||255 | \dmmu_gen.mor1kx_dmmu |mor1kx_dmmu | 239||256 | dtlb_match_regs |mor1kx_true_dpram_sclk | 61||257 | dtlb_translate_regs |mor1kx_true_dpram_sclk_342 | 173||258 | \store_buffer_gen.mor1kx_store_buffer |mor1kx_store_buffer | 162||259 | fifo_ram |mor1kx_simple_dpram_sclk__parameterized1 | 121||260 | mor1kx_rf_cappuccino |mor1kx_rf_cappuccino | 734||261 | rfa |mor1kx_simple_dpram_sclk__parameterized5 | 33||262 | rfb |mor1kx_simple_dpram_sclk__parameterized5_340 | 33||263 | \rfspr_gen.rfspr |mor1kx_simple_dpram_sclk__parameterized5_341 | 1||264 | mor1kx_wb_mux_cappuccino |mor1kx_wb_mux_cappuccino | 111||265 | led |gpo | 2||266 | ni |ni_master | 1028||267 | \multi_channel.receive_arbiter |bus_arbiter | 10||268 | the_combinational_arbiter |arbiter_338 | 2||269 | \w4.one_hot_arb |my_one_hot_arbiter_339 | 2||270 | \multi_channel.send_arbiter |bus_arbiter_330 | 8||271 | the_combinational_arbiter |arbiter_336 | 2||272 | \w4.one_hot_arb |my_one_hot_arbiter_337 | 2||273 | \precap.vc__[0].precap_data_fifo |fwft_fifo__parameterized1 | 11||274 | \precap.vc__[1].precap_data_fifo |fwft_fifo__parameterized1_331 | 13||275 | the_ififo |flit_buffer_332 | 81||276 | \pow2.the_queue |fifo_ram_335 | 49||277 | the_ovc_status |ovc_status | 15||278 | \vc_[0].vc_dma |ni_vc_dma | 226||279 | \vc_[0].wb_slave_registers |ni_vc_wb_slave_regs | 192||280 | \vc_[1].vc_dma |ni_vc_dma_333 | 214||281 | \vc_[1].wb_slave_registers |ni_vc_wb_slave_regs_334 | 224||282 | ram |wb_single_port_ram__parameterized2 | 291||283 | ctrl |wb_bram_ctrl | 226||284 | \burst_wb.bram_ctrl |wb_burst_bram_ctrl | 226||285 | ram_top |single_port_ram_top__parameterized2 | 65||286 | \xilinx_fpga.xilinx_dual.xpm_memory_tdpram_inst |xpm_memory_tdpram__parameterized2 | 64||287 | xpm_memory_base_inst |xpm_memory_base__parameterized2 | 64||288 | ss |clk_source | 17||289 | sync |altera_reset_synchronizer | 17||290 | timer |timer | 185||291 | uart |pronoc_jtag_uart__parameterized2 | 125||292 | uart_hw |pronoc_jtag_uart_hw__parameterized2 | 125||293 | jtag_to_wb_fifo |uart_fifo | 55||294 | wb_to_jtag_fifo |uart_fifo_329 | 61||295 | the_noc |noc | 4409||296 | \tori_noc.mesh_torus_noc |mesh_torus_noc | 4409||297 | \mesh_torus.y_loop[0].x_loop[0].the_router |router | 1108||298 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_239 | 20||299 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_294 | 20||300 | nonspeculative_sw_allocator |nonspec_sw_alloc_295 | 14||301 | \port_loop[0].input_arbiter |swa_input_port_arbiter_308 | 1||302 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_327 | 1||303 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_328 | 1||304 | \port_loop[0].output_arbiter |swa_output_port_arbiter_309 | 2||305 | \rra_m.arb |arbiter__parameterized0_325 | 2||306 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_326 | 2||307 | \port_loop[1].input_arbiter |swa_input_port_arbiter_310 | 1||308 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_323 | 1||309 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_324 | 1||310 | \port_loop[2].output_arbiter |swa_output_port_arbiter_311 | 5||311 | \rra_m.arb |arbiter__parameterized0_321 | 5||312 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_322 | 5||313 | \port_loop[3].output_arbiter |swa_output_port_arbiter_312 | 2||314 | \rra_m.arb |arbiter__parameterized0_319 | 2||315 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_320 | 2||316 | \port_loop[4].input_arbiter |swa_input_port_arbiter_313 | 1||317 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_317 | 1||318 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_318 | 1||319 | \port_loop[4].output_arbiter |swa_output_port_arbiter_314 | 2||320 | \rra_m.arb |arbiter__parameterized0_315 | 2||321 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_316 | 2||322 | \total_vc_loop[0].ovc_arbiter |arbiter_296 | 1||323 | \w4.one_hot_arb |my_one_hot_arbiter_307 | 1||324 | \total_vc_loop[1].ovc_arbiter |arbiter_297 | 1||325 | \w4.one_hot_arb |my_one_hot_arbiter_306 | 1||326 | \total_vc_loop[2].ovc_arbiter |arbiter_298 | 1||327 | \w4.one_hot_arb |my_one_hot_arbiter_305 | 1||328 | \total_vc_loop[3].ovc_arbiter |arbiter_299 | 1||329 | \w4.one_hot_arb |my_one_hot_arbiter_304 | 1||330 | \total_vc_loop[8].ovc_arbiter |arbiter_300 | 1||331 | \w4.one_hot_arb |my_one_hot_arbiter_303 | 1||332 | \total_vc_loop[9].ovc_arbiter |arbiter_301 | 1||333 | \w4.one_hot_arb |my_one_hot_arbiter_302 | 1||334 | the_inout_ports |inout_ports_240 | 1082||335 | \noncanonical.the_credit_counter |credit_counter_241 | 204||336 | \PV_loop2[0].sw_mask |sw_mask_gen_288 | 2||337 | \PV_loop2[1].sw_mask |sw_mask_gen_289 | 2||338 | \PV_loop2[2].sw_mask |sw_mask_gen_290 | 2||339 | \PV_loop2[3].sw_mask |sw_mask_gen_291 | 2||340 | \PV_loop2[8].sw_mask |sw_mask_gen_292 | 9||341 | \PV_loop2[9].sw_mask |sw_mask_gen_293 | 26||342 | the_input_port |input_ports_242 | 858||343 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_243 | 263||344 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_278 | 54||345 | \V_loop[0].lk_dest_fifo |fwft_fifo_279 | 17||346 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_280 | 22||347 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_281 | 48||348 | \V_loop[1].lk_dest_fifo |fwft_fifo_282 | 17||349 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_283 | 15||350 | lk_routing |look_ahead_routing_284 | 10||351 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_287 | 10||352 | \nonspec.the_flit_buffer |flit_buffer_285 | 76||353 | \pow2.the_queue |fifo_ram_286 | 48||354 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_244 | 308||355 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_267 | 55||356 | \V_loop[0].lk_dest_fifo |fwft_fifo_268 | 16||357 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_269 | 19||358 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_270 | 46||359 | \V_loop[1].lk_dest_fifo |fwft_fifo_271 | 16||360 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_272 | 17||361 | lk_routing |look_ahead_routing__parameterized0_273 | 11||362 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized0_277 | 11||363 | \nonspec.the_flit_buffer |flit_buffer_274 | 114||364 | \pow2.the_queue |fifo_ram_276 | 84||365 | the_flit_update |header_flit_update_lk_route_ovc_275 | 10||366 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_245 | 14||367 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_262 | 3||368 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_263 | 1||369 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_264 | 3||370 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_265 | 3||371 | \nonspec.the_flit_buffer |flit_buffer_266 | 4||372 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_246 | 11||373 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_259 | 2||374 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_260 | 2||375 | \nonspec.the_flit_buffer |flit_buffer_261 | 7||376 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_247 | 262||377 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_248 | 18||378 | \V_loop[0].lk_dest_fifo |fwft_fifo_249 | 16||379 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_250 | 16||380 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_251 | 37||381 | \V_loop[1].lk_dest_fifo |fwft_fifo_252 | 16||382 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_253 | 14||383 | lk_routing |look_ahead_routing__parameterized3_254 | 11||384 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized3_258 | 11||385 | \nonspec.the_flit_buffer |flit_buffer_255 | 118||386 | \pow2.the_queue |fifo_ram_257 | 90||387 | the_flit_update |header_flit_update_lk_route_ovc_256 | 12||388 | \mesh_torus.y_loop[0].x_loop[1].the_router |router_0 | 1111||389 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_151 | 22||390 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_204 | 22||391 | nonspeculative_sw_allocator |nonspec_sw_alloc_205 | 16||392 | \port_loop[0].input_arbiter |swa_input_port_arbiter_218 | 1||393 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_237 | 1||394 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_238 | 1||395 | \port_loop[0].output_arbiter |swa_output_port_arbiter_219 | 5||396 | \rra_m.arb |arbiter__parameterized0_235 | 5||397 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_236 | 5||398 | \port_loop[1].output_arbiter |swa_output_port_arbiter_220 | 2||399 | \rra_m.arb |arbiter__parameterized0_233 | 2||400 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_234 | 2||401 | \port_loop[2].output_arbiter |swa_output_port_arbiter_221 | 4||402 | \rra_m.arb |arbiter__parameterized0_231 | 4||403 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_232 | 4||404 | \port_loop[3].input_arbiter |swa_input_port_arbiter_222 | 1||405 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_229 | 1||406 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_230 | 1||407 | \port_loop[4].input_arbiter |swa_input_port_arbiter_223 | 1||408 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_227 | 1||409 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_228 | 1||410 | \port_loop[4].output_arbiter |swa_output_port_arbiter_224 | 2||411 | \rra_m.arb |arbiter__parameterized0_225 | 2||412 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_226 | 2||413 | \total_vc_loop[0].ovc_arbiter |arbiter_206 | 1||414 | \w4.one_hot_arb |my_one_hot_arbiter_217 | 1||415 | \total_vc_loop[1].ovc_arbiter |arbiter_207 | 1||416 | \w4.one_hot_arb |my_one_hot_arbiter_216 | 1||417 | \total_vc_loop[6].ovc_arbiter |arbiter_208 | 1||418 | \w4.one_hot_arb |my_one_hot_arbiter_215 | 1||419 | \total_vc_loop[7].ovc_arbiter |arbiter_209 | 1||420 | \w4.one_hot_arb |my_one_hot_arbiter_214 | 1||421 | \total_vc_loop[8].ovc_arbiter |arbiter_210 | 1||422 | \w4.one_hot_arb |my_one_hot_arbiter_213 | 1||423 | \total_vc_loop[9].ovc_arbiter |arbiter_211 | 1||424 | \w4.one_hot_arb |my_one_hot_arbiter_212 | 1||425 | the_inout_ports |inout_ports_152 | 1083||426 | \noncanonical.the_credit_counter |credit_counter_153 | 209||427 | \PV_loop2[0].sw_mask |sw_mask_gen_198 | 2||428 | \PV_loop2[1].sw_mask |sw_mask_gen_199 | 2||429 | \PV_loop2[6].sw_mask |sw_mask_gen_200 | 2||430 | \PV_loop2[7].sw_mask |sw_mask_gen_201 | 2||431 | \PV_loop2[8].sw_mask |sw_mask_gen_202 | 7||432 | \PV_loop2[9].sw_mask |sw_mask_gen_203 | 32||433 | the_input_port |input_ports_154 | 854||434 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_155 | 262||435 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_188 | 54||436 | \V_loop[0].lk_dest_fifo |fwft_fifo_189 | 17||437 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_190 | 21||438 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_191 | 48||439 | \V_loop[1].lk_dest_fifo |fwft_fifo_192 | 17||440 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_193 | 15||441 | lk_routing |look_ahead_routing_194 | 10||442 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_197 | 10||443 | \nonspec.the_flit_buffer |flit_buffer_195 | 76||444 | \pow2.the_queue |fifo_ram_196 | 48||445 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_156 | 11||446 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_185 | 2||447 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_186 | 2||448 | \nonspec.the_flit_buffer |flit_buffer_187 | 7||449 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_157 | 14||450 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_180 | 3||451 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_181 | 1||452 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_182 | 3||453 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_183 | 3||454 | \nonspec.the_flit_buffer |flit_buffer_184 | 4||455 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_158 | 357||456 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_169 | 52||457 | \V_loop[0].lk_dest_fifo |fwft_fifo_170 | 16||458 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_171 | 19||459 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_172 | 52||460 | \V_loop[1].lk_dest_fifo |fwft_fifo_173 | 16||461 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_174 | 17||462 | lk_routing |look_ahead_routing__parameterized2_175 | 11||463 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized2_179 | 11||464 | \nonspec.the_flit_buffer |flit_buffer_176 | 160||465 | \pow2.the_queue |fifo_ram_178 | 130||466 | the_flit_update |header_flit_update_lk_route_ovc_177 | 10||467 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_159 | 210||468 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_160 | 19||469 | \V_loop[0].lk_dest_fifo |fwft_fifo_161 | 16||470 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_162 | 17||471 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_163 | 27||472 | \V_loop[1].lk_dest_fifo |fwft_fifo_164 | 16||473 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_165 | 15||474 | lk_routing |look_ahead_routing__parameterized3 | 11||475 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized3 | 11||476 | \nonspec.the_flit_buffer |flit_buffer_166 | 73||477 | \pow2.the_queue |fifo_ram_168 | 44||478 | the_flit_update |header_flit_update_lk_route_ovc_167 | 12||479 | \mesh_torus.y_loop[1].x_loop[0].the_router |router_1 | 1099||480 | the_combined_vc_sw_alloc |combined_vc_sw_alloc_63 | 20||481 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator_116 | 20||482 | nonspeculative_sw_allocator |nonspec_sw_alloc_117 | 14||483 | \port_loop[0].input_arbiter |swa_input_port_arbiter_130 | 1||484 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_149 | 1||485 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_150 | 1||486 | \port_loop[0].output_arbiter |swa_output_port_arbiter_131 | 2||487 | \rra_m.arb |arbiter__parameterized0_147 | 2||488 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_148 | 2||489 | \port_loop[1].input_arbiter |swa_input_port_arbiter_132 | 1||490 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_145 | 1||491 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_146 | 1||492 | \port_loop[2].input_arbiter |swa_input_port_arbiter_133 | 1||493 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_143 | 1||494 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_144 | 1||495 | \port_loop[2].output_arbiter |swa_output_port_arbiter_134 | 2||496 | \rra_m.arb |arbiter__parameterized0_141 | 2||497 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_142 | 2||498 | \port_loop[3].output_arbiter |swa_output_port_arbiter_135 | 2||499 | \rra_m.arb |arbiter__parameterized0_139 | 2||500 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_140 | 2||501 | \port_loop[4].output_arbiter |swa_output_port_arbiter_136 | 5||502 | \rra_m.arb |arbiter__parameterized0_137 | 5||503 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_138 | 5||504 | \total_vc_loop[0].ovc_arbiter |arbiter_118 | 1||505 | \w4.one_hot_arb |my_one_hot_arbiter_129 | 1||506 | \total_vc_loop[1].ovc_arbiter |arbiter_119 | 1||507 | \w4.one_hot_arb |my_one_hot_arbiter_128 | 1||508 | \total_vc_loop[2].ovc_arbiter |arbiter_120 | 1||509 | \w4.one_hot_arb |my_one_hot_arbiter_127 | 1||510 | \total_vc_loop[3].ovc_arbiter |arbiter_121 | 1||511 | \w4.one_hot_arb |my_one_hot_arbiter_126 | 1||512 | \total_vc_loop[4].ovc_arbiter |arbiter_122 | 1||513 | \w4.one_hot_arb |my_one_hot_arbiter_125 | 1||514 | \total_vc_loop[5].ovc_arbiter |arbiter_123 | 1||515 | \w4.one_hot_arb |my_one_hot_arbiter_124 | 1||516 | the_inout_ports |inout_ports_64 | 1073||517 | \noncanonical.the_credit_counter |credit_counter_65 | 215||518 | \PV_loop2[0].sw_mask |sw_mask_gen_110 | 2||519 | \PV_loop2[1].sw_mask |sw_mask_gen_111 | 2||520 | \PV_loop2[2].sw_mask |sw_mask_gen_112 | 2||521 | \PV_loop2[3].sw_mask |sw_mask_gen_113 | 2||522 | \PV_loop2[4].sw_mask |sw_mask_gen_114 | 26||523 | \PV_loop2[5].sw_mask |sw_mask_gen_115 | 8||524 | the_input_port |input_ports_66 | 838||525 | \port_loop[0].the_input_queue_per_port |input_queue_per_port_67 | 225||526 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_100 | 38||527 | \V_loop[0].lk_dest_fifo |fwft_fifo_101 | 17||528 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_102 | 16||529 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_103 | 26||530 | \V_loop[1].lk_dest_fifo |fwft_fifo_104 | 17||531 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_105 | 17||532 | lk_routing |look_ahead_routing_106 | 12||533 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing_109 | 12||534 | \nonspec.the_flit_buffer |flit_buffer_107 | 78||535 | \pow2.the_queue |fifo_ram_108 | 48||536 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0_68 | 345||537 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_91 | 68||538 | \V_loop[0].lk_dest_fifo |fwft_fifo_92 | 17||539 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_93 | 16||540 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_94 | 67||541 | \V_loop[1].lk_dest_fifo |fwft_fifo_95 | 17||542 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_96 | 18||543 | lk_routing |look_ahead_routing__parameterized0 | 9||544 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized0 | 9||545 | \nonspec.the_flit_buffer |flit_buffer_97 | 108||546 | \pow2.the_queue |fifo_ram_99 | 78||547 | the_flit_update |header_flit_update_lk_route_ovc_98 | 21||548 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1_69 | 246||549 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_80 | 20||550 | \V_loop[0].lk_dest_fifo |fwft_fifo_81 | 16||551 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_82 | 15||552 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_83 | 19||553 | \V_loop[1].lk_dest_fifo |fwft_fifo_84 | 16||554 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_85 | 14||555 | lk_routing |look_ahead_routing__parameterized1_86 | 11||556 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized1_90 | 11||557 | \nonspec.the_flit_buffer |flit_buffer_87 | 115||558 | \pow2.the_queue |fifo_ram_89 | 82||559 | the_flit_update |header_flit_update_lk_route_ovc_88 | 16||560 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2_70 | 10||561 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_77 | 2||562 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_78 | 2||563 | \nonspec.the_flit_buffer |flit_buffer_79 | 6||564 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3_71 | 12||565 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_72 | 2||566 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_73 | 1||567 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_74 | 2||568 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_75 | 3||569 | \nonspec.the_flit_buffer |flit_buffer_76 | 4||570 | \mesh_torus.y_loop[1].x_loop[1].the_router |router_2 | 1091||571 | the_combined_vc_sw_alloc |combined_vc_sw_alloc | 22||572 | \nonspec.cmb_v1.nonspec_comb |comb_nonspec_allocator | 22||573 | nonspeculative_sw_allocator |nonspec_sw_alloc | 16||574 | \port_loop[0].input_arbiter |swa_input_port_arbiter | 1||575 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_61 | 1||576 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_62 | 1||577 | \port_loop[0].output_arbiter |swa_output_port_arbiter | 5||578 | \rra_m.arb |arbiter__parameterized0_59 | 5||579 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_60 | 5||580 | \port_loop[1].output_arbiter |swa_output_port_arbiter_48 | 2||581 | \rra_m.arb |arbiter__parameterized0_57 | 2||582 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_58 | 2||583 | \port_loop[2].input_arbiter |swa_input_port_arbiter_49 | 1||584 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en_55 | 1||585 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en_56 | 1||586 | \port_loop[2].output_arbiter |swa_output_port_arbiter_50 | 2||587 | \rra_m.arb |arbiter__parameterized0_53 | 2||588 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0_54 | 2||589 | \port_loop[3].input_arbiter |swa_input_port_arbiter_51 | 1||590 | \rra_m.arbiter_ext_en.arb |arbiter_priority_en | 1||591 | \w4.one_hot_arb |my_one_hot_arbiter_priority_en | 1||592 | \port_loop[4].output_arbiter |swa_output_port_arbiter_52 | 4||593 | \rra_m.arb |arbiter__parameterized0 | 4||594 | \w4.one_hot_arb |my_one_hot_arbiter__parameterized0 | 4||595 | \total_vc_loop[0].ovc_arbiter |arbiter | 1||596 | \w4.one_hot_arb |my_one_hot_arbiter_47 | 1||597 | \total_vc_loop[1].ovc_arbiter |arbiter_38 | 1||598 | \w4.one_hot_arb |my_one_hot_arbiter_46 | 1||599 | \total_vc_loop[4].ovc_arbiter |arbiter_39 | 1||600 | \w4.one_hot_arb |my_one_hot_arbiter_45 | 1||601 | \total_vc_loop[5].ovc_arbiter |arbiter_40 | 1||602 | \w4.one_hot_arb |my_one_hot_arbiter_44 | 1||603 | \total_vc_loop[6].ovc_arbiter |arbiter_41 | 1||604 | \w4.one_hot_arb |my_one_hot_arbiter_43 | 1||605 | \total_vc_loop[7].ovc_arbiter |arbiter_42 | 1||606 | \w4.one_hot_arb |my_one_hot_arbiter | 1||607 | the_inout_ports |inout_ports | 1062||608 | \noncanonical.the_credit_counter |credit_counter | 217||609 | \PV_loop2[0].sw_mask |sw_mask_gen | 6||610 | \PV_loop2[1].sw_mask |sw_mask_gen_33 | 4||611 | \PV_loop2[4].sw_mask |sw_mask_gen_34 | 25||612 | \PV_loop2[5].sw_mask |sw_mask_gen_35 | 8||613 | \PV_loop2[6].sw_mask |sw_mask_gen_36 | 2||614 | \PV_loop2[7].sw_mask |sw_mask_gen_37 | 2||615 | the_input_port |input_ports | 825||616 | \port_loop[0].the_input_queue_per_port |input_queue_per_port | 204||617 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_25 | 18||618 | \V_loop[0].lk_dest_fifo |fwft_fifo_26 | 17||619 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_27 | 14||620 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_28 | 31||621 | \V_loop[1].lk_dest_fifo |fwft_fifo_29 | 17||622 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_30 | 16||623 | lk_routing |look_ahead_routing | 10||624 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing | 10||625 | \nonspec.the_flit_buffer |flit_buffer_31 | 77||626 | \pow2.the_queue |fifo_ram_32 | 48||627 | \port_loop[1].the_input_queue_per_port |input_queue_per_port__parameterized0 | 11||628 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_21 | 2||629 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_22 | 1||630 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_23 | 2||631 | \nonspec.the_flit_buffer |flit_buffer_24 | 6||632 | \port_loop[2].the_input_queue_per_port |input_queue_per_port__parameterized1 | 251||633 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_12 | 17||634 | \V_loop[0].lk_dest_fifo |fwft_fifo_13 | 16||635 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_14 | 15||636 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_15 | 28||637 | \V_loop[1].lk_dest_fifo |fwft_fifo_16 | 16||638 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_17 | 15||639 | lk_routing |look_ahead_routing__parameterized1 | 11||640 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized1 | 11||641 | \nonspec.the_flit_buffer |flit_buffer_18 | 117||642 | \pow2.the_queue |fifo_ram_20 | 84||643 | the_flit_update |header_flit_update_lk_route_ovc_19 | 12||644 | \port_loop[3].the_input_queue_per_port |input_queue_per_port__parameterized2 | 347||645 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo_5 | 63||646 | \V_loop[0].lk_dest_fifo |fwft_fifo_6 | 16||647 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0_7 | 16||648 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_8 | 68||649 | \V_loop[1].lk_dest_fifo |fwft_fifo_9 | 16||650 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_10 | 18||651 | lk_routing |look_ahead_routing__parameterized2 | 11||652 | \mesh_torus.look_ahead_route |mesh_torus_look_ahead_routing__parameterized2 | 11||653 | \nonspec.the_flit_buffer |flit_buffer_11 | 108||654 | \pow2.the_queue |fifo_ram | 78||655 | the_flit_update |header_flit_update_lk_route_ovc | 27||656 | \port_loop[4].the_input_queue_per_port |input_queue_per_port__parameterized3 | 12||657 | \V_loop[0].dtrmn_dest.dest_fifo |fwft_fifo | 2||658 | \V_loop[0].tail_fifo |fwft_fifo__parameterized0 | 1||659 | \V_loop[1].dtrmn_dest.dest_fifo |fwft_fifo_3 | 2||660 | \V_loop[1].tail_fifo |fwft_fifo__parameterized0_4 | 3||661 | \nonspec.the_flit_buffer |flit_buffer | 4|+------+-------------------------------------------------------------+--------------------------------------------------+------+---------------------------------------------------------------------------------