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<h1>alu Module Reference</h1> </div>
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<p>Arithmetic and Logic Unit.
<a href="#_details">More...</a></p>
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Inheritance diagram for alu:<!-- endSectionHeader --></div>
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<p><a href="classalu-members.html">List of all members.</a></p>
<table class="memberdecls">
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a833db0d5eda614d712b846b259c0f4d3">ALWAYS_30</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classalu.html#a36f87886602a9c47db7a8701a6bdce46">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classalu.html#a220b548148cb459c8ff39b2d483dcecd">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Defines"></a>
Defines</h2></td></tr>
<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a5b1a1cc35b92a5b359102232856eacc1">Sm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b00</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b01</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#a395ade4366075f31f5f36079483599fd">operand2</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a50ba636de1e4c3986cdd2a6d7d5779d3">Dm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b00</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b01</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#ad280f57c61676d08ef5dd730adc7ccd6">operand1</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a427db1cde5547577da8b980693d9bf64">Rm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b00</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b01</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a23a70b72cb751afcb0b4fd2c1adfe24c">Z</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b00</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">8'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></b> <span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">2'b01</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">16'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">32'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a36f87886602a9c47db7a8701a6bdce46">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a220b548148cb459c8ff39b2d483dcecd">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a8e313062d18caaf2819d3d7c66510db5">address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ae8afa27ca5038ed0fa84bad168f47e3c">ir</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ad280f57c61676d08ef5dd730adc7ccd6">operand1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a395ade4366075f31f5f36079483599fd">operand2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a457656565c789b00661f94759e32a480">interrupt_mask</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a62b9ab4712b3d5a3b126dac400ee2f51">alu_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#abc0978adad3a64f5ec561063e5373a66">sr</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a3adf282aaf4286e6ba69d45a1b88ce51">special</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
<tr><td colspan="2"><h2><a name="Module Instances"></a>
Module Instances</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a663a13286f43eb65ddc36752990daf91">lpm_divide::divu_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a63937f247c96f23cecbf16343afc85c6">lpm_divide::divs_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a971600ecbf5096805b63eedb9e8c57e2">lpm_mult::mulu_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a26728d930b96d3b4eb3777152250aa48">lpm_mult::muls_inst</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#aa952272b6e8aa9701870b6a6c7927db2">divu_quotient</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a023cbaaa8756d8106ae8e83d9d7229bf">divu_remainder</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a8932104dcef8211591deffa08ac0a5e2">divs_quotient</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#aed73e62ae69c111fa7afee3ce9d423d2">divs_remainder</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a8183678443b594c9ed8737caf046220f">mulu_result</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a63ae5f9acc7ef3206f9de941f2960fd1">muls_result</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#adb8748a2e062573abf7a979dd4518b2a">interrupt_mask_copy</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ab4460ee9b3a684b5c92ef13a19940720">was_interrupt</a> </td></tr>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>Arithmetic and Logic Unit. </p>
<p>The alu module is responsible for performing all of the arithmetic and logic operations of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> processor. It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into a result 32-bit register. This register is located in the alu module.</p>
<p>The alu module also contains the status register (SR) with the condition code register. The microcode decides what operation the alu performs. </p>
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02557">2557</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a833db0d5eda614d712b846b259c0f4d3"></a><!-- doxytag: member="alu::ALWAYS_30" ref="a833db0d5eda614d712b846b259c0f4d3" args="clock, reset_n" -->
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_30 <td></td>
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a36f87886602a9c47db7a8701a6bdce46">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
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<td class="paramkey"></td>
<td></td>
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a220b548148cb459c8ff39b2d483dcecd">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02676">2676</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="a36f87886602a9c47db7a8701a6bdce46"></a><!-- doxytag: member="alu::clock" ref="a36f87886602a9c47db7a8701a6bdce46" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a36f87886602a9c47db7a8701a6bdce46">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02558">2558</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a220b548148cb459c8ff39b2d483dcecd"></a><!-- doxytag: member="alu::reset_n" ref="a220b548148cb459c8ff39b2d483dcecd" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a220b548148cb459c8ff39b2d483dcecd">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02559">2559</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a8e313062d18caaf2819d3d7c66510db5"></a><!-- doxytag: member="alu::address" ref="a8e313062d18caaf2819d3d7c66510db5" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a8e313062d18caaf2819d3d7c66510db5">address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02562">2562</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="ae8afa27ca5038ed0fa84bad168f47e3c"></a><!-- doxytag: member="alu::ir" ref="ae8afa27ca5038ed0fa84bad168f47e3c" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ae8afa27ca5038ed0fa84bad168f47e3c">ir</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02564">2564</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a40e8b48bd8a651f3425be48e829b2176"></a><!-- doxytag: member="alu::size" ref="a40e8b48bd8a651f3425be48e829b2176" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a40e8b48bd8a651f3425be48e829b2176">size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02566">2566</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="ad280f57c61676d08ef5dd730adc7ccd6"></a><!-- doxytag: member="alu::operand1" ref="ad280f57c61676d08ef5dd730adc7ccd6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ad280f57c61676d08ef5dd730adc7ccd6">operand1</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02568">2568</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a395ade4366075f31f5f36079483599fd"></a><!-- doxytag: member="alu::operand2" ref="a395ade4366075f31f5f36079483599fd" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a395ade4366075f31f5f36079483599fd">operand2</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02569">2569</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a457656565c789b00661f94759e32a480"></a><!-- doxytag: member="alu::interrupt_mask" ref="a457656565c789b00661f94759e32a480" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a457656565c789b00661f94759e32a480">interrupt_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02571">2571</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a62b9ab4712b3d5a3b126dac400ee2f51"></a><!-- doxytag: member="alu::alu_control" ref="a62b9ab4712b3d5a3b126dac400ee2f51" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a62b9ab4712b3d5a3b126dac400ee2f51">alu_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02572">2572</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="abc0978adad3a64f5ec561063e5373a66"></a><!-- doxytag: member="alu::sr" ref="abc0978adad3a64f5ec561063e5373a66" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#abc0978adad3a64f5ec561063e5373a66">sr</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02574">2574</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a70be5f9073bc1a2461372f1d95d0fb7d"></a><!-- doxytag: member="alu::result" ref="a70be5f9073bc1a2461372f1d95d0fb7d" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a70be5f9073bc1a2461372f1d95d0fb7d">result</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02575">2575</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="a3adf282aaf4286e6ba69d45a1b88ce51"></a><!-- doxytag: member="alu::special" ref="a3adf282aaf4286e6ba69d45a1b88ce51" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a3adf282aaf4286e6ba69d45a1b88ce51">special</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02576">2576</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="aa952272b6e8aa9701870b6a6c7927db2"></a><!-- doxytag: member="alu::divu_quotient" ref="aa952272b6e8aa9701870b6a6c7927db2" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aa952272b6e8aa9701870b6a6c7927db2">divu_quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02579">2579</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a023cbaaa8756d8106ae8e83d9d7229bf"></a><!-- doxytag: member="alu::divu_remainder" ref="a023cbaaa8756d8106ae8e83d9d7229bf" args="wire[15:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a023cbaaa8756d8106ae8e83d9d7229bf">divu_remainder</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02580">2580</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8932104dcef8211591deffa08ac0a5e2"></a><!-- doxytag: member="alu::divs_quotient" ref="a8932104dcef8211591deffa08ac0a5e2" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a8932104dcef8211591deffa08ac0a5e2">divs_quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02581">2581</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
<a class="anchor" id="aed73e62ae69c111fa7afee3ce9d423d2"></a><!-- doxytag: member="alu::divs_remainder" ref="aed73e62ae69c111fa7afee3ce9d423d2" args="wire[15:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aed73e62ae69c111fa7afee3ce9d423d2">divs_remainder</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02582">2582</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8183678443b594c9ed8737caf046220f"></a><!-- doxytag: member="alu::mulu_result" ref="a8183678443b594c9ed8737caf046220f" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a8183678443b594c9ed8737caf046220f">mulu_result</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02583">2583</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a63ae5f9acc7ef3206f9de941f2960fd1"></a><!-- doxytag: member="alu::muls_result" ref="a63ae5f9acc7ef3206f9de941f2960fd1" args="wire[31:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a63ae5f9acc7ef3206f9de941f2960fd1">muls_result</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02584">2584</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a663a13286f43eb65ddc36752990daf91"></a><!-- doxytag: member="alu::lpm_divide" ref="a663a13286f43eb65ddc36752990daf91" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a663a13286f43eb65ddc36752990daf91">lpm_divide</a></span> <b><span class="vhdlchar">divu_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02601">2601</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a63937f247c96f23cecbf16343afc85c6"></a><!-- doxytag: member="alu::lpm_divide" ref="a63937f247c96f23cecbf16343afc85c6" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a63937f247c96f23cecbf16343afc85c6">lpm_divide</a></span> <b><span class="vhdlchar">divs_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02618">2618</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a971600ecbf5096805b63eedb9e8c57e2"></a><!-- doxytag: member="alu::lpm_mult" ref="a971600ecbf5096805b63eedb9e8c57e2" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a971600ecbf5096805b63eedb9e8c57e2">lpm_mult</a></span> <b><span class="vhdlchar">mulu_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02634">2634</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a26728d930b96d3b4eb3777152250aa48"></a><!-- doxytag: member="alu::lpm_mult" ref="a26728d930b96d3b4eb3777152250aa48" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a26728d930b96d3b4eb3777152250aa48">lpm_mult</a></span> <b><span class="vhdlchar">muls_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<div class="memdoc">
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02648">2648</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a5b1a1cc35b92a5b359102232856eacc1">Sm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02663">2663</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a50ba636de1e4c3986cdd2a6d7d5779d3">Dm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02665">2665</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a427db1cde5547577da8b980693d9bf64"></a><!-- doxytag: member="alu::Rm" ref="a427db1cde5547577da8b980693d9bf64" args="((size==2'b00)?result[7]:(size==2'b01)?result[15]:result[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a427db1cde5547577da8b980693d9bf64">Rm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02667">2667</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a23a70b72cb751afcb0b4fd2c1adfe24c">Z</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02669">2669</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="adb8748a2e062573abf7a979dd4518b2a"></a><!-- doxytag: member="alu::interrupt_mask_copy" ref="adb8748a2e062573abf7a979dd4518b2a" args="reg[2:0]" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#adb8748a2e062573abf7a979dd4518b2a">interrupt_mask_copy</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[2:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02673">2673</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ab4460ee9b3a684b5c92ef13a19940720"></a><!-- doxytag: member="alu::was_interrupt" ref="ab4460ee9b3a684b5c92ef13a19940720" args="reg" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab4460ee9b3a684b5c92ef13a19940720">was_interrupt</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02674">2674</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:19 for aoOCS by 
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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