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<a href="#Inputs">Inputs</a> &#124;
<a href="#Outputs">Outputs</a> &#124;
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<h1>bus_ssram Module Reference</h1>  </div>
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<p><p>IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface. </p>
 
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<p><a href="classbus__ssram-members.html">List of all members.</a></p>
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
Always Constructs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a6f9c73deb7569c415de5ce9593a44a79">ALWAYS_61</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
<tr><td colspan="2"><h2><a name="Inputs"></a>
Inputs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a2c671a3dc4da1d00f8a48ae8ed545934">burst_write_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">ADR_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">20</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">CYC_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">WE_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ae4f1b8a90123ceac3fded15df24e3bd3">SEL_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">STB_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ad83abd19cd21950a7e5abcd0068463a5">DAT_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">Direct drv_ssram read/write burst DMA for ocs_video and drv_vga</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Inouts"></a>
Inouts</h2></td></tr>
 <tr><td colspan="2"><div class="groupHeader">IS61LPS51236A pipelined SSRAM hardware interface</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><h2><a name="Outputs"></a>
Outputs</h2></td></tr>
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">DAT_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">Direct drv_ssram read/write burst DMA for ocs_video and drv_vga</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ae9dc8c4cc4309b39f5d1aebaeded912a">burst_read_vga_ready</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a838aea80fed0e9a079d844ffd8ce3d12">burst_read_video_ready</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
<tr><td colspan="2"><div class="groupHeader">IS61LPS51236A pipelined SSRAM hardware interface</div></td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">18</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Parameters"></a>
Parameters</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#ae3aad805c7623cf48b1dc1b34dd51dbd">S_VW0</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">4'd1</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__ssram.html#a11872fcb25d808ba613e41904ff6e066">S_VW4</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">4'd5</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
Signals</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> </td></tr>
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> </td></tr>
</table>
<hr/><a name="_details"></a><h2>Detailed Description</h2>
<p>IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface. </p>
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00031">31</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
<hr/><h2>Member Function Documentation</h2>
<a class="anchor" id="a6f9c73deb7569c415de5ce9593a44a79"></a><!-- doxytag: member="bus_ssram::ALWAYS_61" ref="a6f9c73deb7569c415de5ce9593a44a79" args="clk_30, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_61          <td></td>
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
        </tr>
<code> [Always Construct]</code></td>
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</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00130">130</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
</div>
</div>
<hr/><h2>Member Data Documentation</h2>
<a class="anchor" id="adf48cd47cdb3d0ab37c4f679d47b3ece"></a><!-- doxytag: member="bus_ssram::clk_30" ref="adf48cd47cdb3d0ab37c4f679d47b3ece" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00034">34</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="af7d17848e6f2da5ae9db4a6072dfb9a9"></a><!-- doxytag: member="bus_ssram::reset_n" ref="af7d17848e6f2da5ae9db4a6072dfb9a9" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00035">35</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a56b6627a4fb74424900848ab0d094141"></a><!-- doxytag: member="bus_ssram::ADR_I" ref="a56b6627a4fb74424900848ab0d094141" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">20</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
        </tr>
      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00040">40</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a8ec0e74cb4fdeeff97eb86626b94e3af"></a><!-- doxytag: member="bus_ssram::CYC_I" ref="a8ec0e74cb4fdeeff97eb86626b94e3af" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00041">41</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a88849a8c056fffdad33d71b2abaa0f03"></a><!-- doxytag: member="bus_ssram::WE_I" ref="a88849a8c056fffdad33d71b2abaa0f03" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00042">42</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ae4f1b8a90123ceac3fded15df24e3bd3"></a><!-- doxytag: member="bus_ssram::SEL_I" ref="ae4f1b8a90123ceac3fded15df24e3bd3" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ae4f1b8a90123ceac3fded15df24e3bd3">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00043">43</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="adae0a05e495069a4351965372c3634c8"></a><!-- doxytag: member="bus_ssram::STB_I" ref="adae0a05e495069a4351965372c3634c8" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00044">44</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ad83abd19cd21950a7e5abcd0068463a5"></a><!-- doxytag: member="bus_ssram::DAT_I" ref="ad83abd19cd21950a7e5abcd0068463a5" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ad83abd19cd21950a7e5abcd0068463a5">DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00045">45</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a78163aefbe6bb0d6f809c7e01b93967b"></a><!-- doxytag: member="bus_ssram::DAT_O" ref="a78163aefbe6bb0d6f809c7e01b93967b" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">DAT_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
        </tr>
      </table>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00046">46</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="af87a2d46e88cd2ccf90487f261366aba"></a><!-- doxytag: member="bus_ssram::ACK_O" ref="af87a2d46e88cd2ccf90487f261366aba" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00047">47</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ad29520a0905218b5c01253c99b6791a3"></a><!-- doxytag: member="bus_ssram::burst_read_vga_request" ref="ad29520a0905218b5c01253c99b6791a3" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00053">53</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ae9ae32b3d42fa1482fa788059b4b65df"></a><!-- doxytag: member="bus_ssram::burst_read_vga_address" ref="ae9ae32b3d42fa1482fa788059b4b65df" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00054">54</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ae9dc8c4cc4309b39f5d1aebaeded912a"></a><!-- doxytag: member="bus_ssram::burst_read_vga_ready" ref="ae9dc8c4cc4309b39f5d1aebaeded912a" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ae9dc8c4cc4309b39f5d1aebaeded912a">burst_read_vga_ready</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00055">55</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a2cc4e33e7bd7ee3d0ad1ac0a743bead3"></a><!-- doxytag: member="bus_ssram::burst_read_video_request" ref="a2cc4e33e7bd7ee3d0ad1ac0a743bead3" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00057">57</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ab4c5fe3d23c0df0ab43247a1639d8fef"></a><!-- doxytag: member="bus_ssram::burst_read_video_address" ref="ab4c5fe3d23c0df0ab43247a1639d8fef" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">burst_read_video_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00058">58</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a838aea80fed0e9a079d844ffd8ce3d12"></a><!-- doxytag: member="bus_ssram::burst_read_video_ready" ref="a838aea80fed0e9a079d844ffd8ce3d12" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a838aea80fed0e9a079d844ffd8ce3d12">burst_read_video_ready</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00059">59</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ae09f95f879e5dbaeaf569cd7b7949acd"></a><!-- doxytag: member="bus_ssram::burst_read_data" ref="ae09f95f879e5dbaeaf569cd7b7949acd" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00061">61</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a41716375d8a472181176cfe136044168"></a><!-- doxytag: member="bus_ssram::burst_write_request" ref="a41716375d8a472181176cfe136044168" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00065">65</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a2c671a3dc4da1d00f8a48ae8ed545934"></a><!-- doxytag: member="bus_ssram::burst_write_address" ref="a2c671a3dc4da1d00f8a48ae8ed545934" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a2c671a3dc4da1d00f8a48ae8ed545934">burst_write_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00066">66</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00067">67</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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</div>
<a class="anchor" id="a6a47c16f84aa2e8aafcf02afbc52b57b"></a><!-- doxytag: member="bus_ssram::burst_write_data" ref="a6a47c16f84aa2e8aafcf02afbc52b57b" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00068">68</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a28c27b19916c54b3e868369aac6f6b9a"></a><!-- doxytag: member="bus_ssram::ssram_address" ref="a28c27b19916c54b3e868369aac6f6b9a" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">18</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00073">73</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ac105e20d6da178b2822b3e87238ae6dc"></a><!-- doxytag: member="bus_ssram::ssram_oe_n" ref="ac105e20d6da178b2822b3e87238ae6dc" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00074">74</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a99f42b3013302ad54129da325e2c0410"></a><!-- doxytag: member="bus_ssram::ssram_writeen_n" ref="a99f42b3013302ad54129da325e2c0410" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00075">75</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a66f9e3c03173432f2950e141e42e47ee"></a><!-- doxytag: member="bus_ssram::ssram_byteen_n" ref="a66f9e3c03173432f2950e141e42e47ee" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00076">76</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a1e624978ad4e4f2149e7980d65b0612d"></a><!-- doxytag: member="bus_ssram::ssram_adsp_n" ref="a1e624978ad4e4f2149e7980d65b0612d" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a1e624978ad4e4f2149e7980d65b0612d">ssram_adsp_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00077">77</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a6e1a75c4a8c1c0a94bd2ec20430a56d3"></a><!-- doxytag: member="bus_ssram::ssram_clk" ref="a6e1a75c4a8c1c0a94bd2ec20430a56d3" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a6e1a75c4a8c1c0a94bd2ec20430a56d3">ssram_clk</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00078">78</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a71ea972c05cab98195ec72ed2bce3b7f"></a><!-- doxytag: member="bus_ssram::ssram_globalw_n" ref="a71ea972c05cab98195ec72ed2bce3b7f" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a71ea972c05cab98195ec72ed2bce3b7f">ssram_globalw_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00079">79</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="acea0b5e48c266c75112e372048947204"></a><!-- doxytag: member="bus_ssram::ssram_advance_n" ref="acea0b5e48c266c75112e372048947204" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00080">80</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a21d0bd68b7b790eb45a03c6992c92a9f"></a><!-- doxytag: member="bus_ssram::ssram_adsc_n" ref="a21d0bd68b7b790eb45a03c6992c92a9f" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00081">81</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a908103f5f1aafa62a9fdcebc83094ebc"></a><!-- doxytag: member="bus_ssram::ssram_ce1_n" ref="a908103f5f1aafa62a9fdcebc83094ebc" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a908103f5f1aafa62a9fdcebc83094ebc">ssram_ce1_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00082">82</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="abc78633b174512e8f12168c05d6484b4"></a><!-- doxytag: member="bus_ssram::ssram_ce2" ref="abc78633b174512e8f12168c05d6484b4" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#abc78633b174512e8f12168c05d6484b4">ssram_ce2</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00083">83</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a926a811b6e4121644e869fe13899b4c5"></a><!-- doxytag: member="bus_ssram::ssram_ce3_n" ref="a926a811b6e4121644e869fe13899b4c5" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a926a811b6e4121644e869fe13899b4c5">ssram_ce3_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00084">84</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ad69f5f977e8c5fb7875d1a69fee22d72"></a><!-- doxytag: member="bus_ssram::ssram_data" ref="ad69f5f977e8c5fb7875d1a69fee22d72" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">35</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Inout]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00085">85</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="af1d128d90eced18c7e7f2789ac9046a9"></a><!-- doxytag: member="bus_ssram::ssram_data_oe" ref="af1d128d90eced18c7e7f2789ac9046a9" args="reg" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00096">96</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a3493866f2c0fa328bc914ee77192bf2e"></a><!-- doxytag: member="bus_ssram::ssram_data_reg" ref="a3493866f2c0fa328bc914ee77192bf2e" args="reg[35:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[35:0]]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00097">97</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a535aefa25808f58b42ac5a1654d56610"></a><!-- doxytag: member="bus_ssram::burst_address" ref="a535aefa25808f58b42ac5a1654d56610" args="reg[18:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[18:0]]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00100">100</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a63750a3306096cd8e7076802d4eb57dd"></a><!-- doxytag: member="bus_ssram::burst_read_select" ref="a63750a3306096cd8e7076802d4eb57dd" args="reg" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00102">102</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a129b5bd32f618b59b3e59264de9726e5"></a><!-- doxytag: member="bus_ssram::burst_read_ready" ref="a129b5bd32f618b59b3e59264de9726e5" args="reg" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00103">103</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ac5e689c9e42fe9b1335117fd5df37775"></a><!-- doxytag: member="bus_ssram::burst_read_low_address" ref="ac5e689c9e42fe9b1335117fd5df37775" args="reg[3:2]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[3:2]]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00108">108</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a4bb8b3742d85ee88a72833d1facf6d4f"></a><!-- doxytag: member="bus_ssram::burst_read_one_loop" ref="a4bb8b3742d85ee88a72833d1facf6d4f" args="reg" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00109">109</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a4ec3a06c44c4a4bd8f83b27bce22cc6a"></a><!-- doxytag: member="bus_ssram::burst_read_request" ref="a4ec3a06c44c4a4bd8f83b27bce22cc6a" args="wire" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00110">110</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a07ff3477e013ed4dfa2439589c118202"></a><!-- doxytag: member="bus_ssram::state" ref="a07ff3477e013ed4dfa2439589c118202" args="reg[3:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[3:0]]</code></td>
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00113">113</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a858c46d836e9106fd17cfcae0529039e"></a><!-- doxytag: member="bus_ssram::S_IDLE" ref="a858c46d836e9106fd17cfcae0529039e" args="4'd0" -->
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<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ae3aad805c7623cf48b1dc1b34dd51dbd"></a><!-- doxytag: member="bus_ssram::S_VW0" ref="ae3aad805c7623cf48b1dc1b34dd51dbd" args="4'd1" -->
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="ade6dc31a79364db517a437bd49aca37a"></a><!-- doxytag: member="bus_ssram::S_VW1" ref="ade6dc31a79364db517a437bd49aca37a" args="4'd2" -->
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a087aee8fa77cb6c2f662118321e09871"></a><!-- doxytag: member="bus_ssram::S_VR3" ref="a087aee8fa77cb6c2f662118321e09871" args="4'd8" -->
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="a007e4900fdab9ae822d87670bdebfb0a"></a><!-- doxytag: member="bus_ssram::S_VR4" ref="a007e4900fdab9ae822d87670bdebfb0a" args="4'd9" -->
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<a class="anchor" id="aa5e59d0bad76d805d61cfcd307af35f8"></a><!-- doxytag: member="bus_ssram::S_R3" ref="aa5e59d0bad76d805d61cfcd307af35f8" args="4'd12" -->
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</div>
<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<div class="memdoc">
 
<p>Definition at line <a class="el" href="bus__ssram_8v_source.html#l00114">114</a> of file <a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a>.</p>
 
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<hr/>The documentation for this class was generated from the following file:<ul>
<li><a class="el" href="bus__ssram_8v_source.html">bus_ssram.v</a></li>
</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
<a href="http://www.doxygen.org/index.html">
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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