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<h1>drv_debug.v</h1> </div>
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<a href="drv__debug_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/* </span>
<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
<a name="l00003"></a>00003 <span class="keyword"> </span>
<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
<a name="l00006"></a>00006 <span class="keyword"> </span>
<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
<a name="l00009"></a>00009 <span class="keyword"> </span>
<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
<a name="l00013"></a>00013 <span class="keyword"> </span>
<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
<a name="l00023"></a>00023 <span class="keyword"> */</span>
<a name="l00024"></a>00024
<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
<a name="l00026"></a>00026 <span class="keyword"> \brief Switches and hex leds driver for debug purposes.</span>
<a name="l00027"></a>00027 <span class="keyword"> */</span>
<a name="l00028"></a>00028
<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief drv_debug.v</span>
<a name="l00030"></a>00030 <span class="keyword">*/</span>
<a name="l00031"></a><a class="code" href="classdrv__debug.html">00031</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdrv__debug.html">drv_debug</a>(
<a name="l00032"></a>00032 <span class="keyword">//% \name Clock and reset
</span>
<a name="l00033"></a>00033 <span class="keyword">//% @{</span>
<a name="l00034"></a><a class="code" href="classdrv__debug.html#a7e36153a71f34792696d16581a6d5f67">00034</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdrv__debug.html#a7e36153a71f34792696d16581a6d5f67">CLK_I</a>,
<a name="l00035"></a><a class="code" href="classdrv__debug.html#acd52a7205cfc84d2188f33227e734941">00035</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdrv__debug.html#acd52a7205cfc84d2188f33227e734941">reset_n</a>,
<a name="l00036"></a>00036 <span class="keyword">//% @}</span>
<a name="l00037"></a>00037
<a name="l00038"></a>00038 <span class="keyword">//% \name Internal debug signals
</span>
<a name="l00039"></a>00039 <span class="keyword">//% @{</span>
<a name="l00040"></a><a class="code" href="classdrv__debug.html#abea03e7c35c90ebd53d600056c06cbb5">00040</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classdrv__debug.html#abea03e7c35c90ebd53d600056c06cbb5">master_adr_o</a>,
<a name="l00041"></a><a class="code" href="classdrv__debug.html#a458757362a58ddbbe763586cb38419d0">00041</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a458757362a58ddbbe763586cb38419d0">debug_pc</a>,
<a name="l00042"></a><a class="code" href="classdrv__debug.html#a406932e72315d7f81c77d0179d3d564f">00042</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a406932e72315d7f81c77d0179d3d564f">debug_syscon</a>,
<a name="l00043"></a><a class="code" href="classdrv__debug.html#ad91c26028449d56aa73ee49500f7bce6">00043</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#ad91c26028449d56aa73ee49500f7bce6">debug_track</a>,
<a name="l00044"></a>00044 <span class="keyword">//% @}</span>
<a name="l00045"></a>00045
<a name="l00046"></a>00046 <span class="keyword">//% \name Switches and hex leds hardware interface
</span>
<a name="l00047"></a>00047 <span class="keyword">//% @{</span>
<a name="l00048"></a>00048 <span class="keyword">// hex output</span>
<a name="l00049"></a><a class="code" href="classdrv__debug.html#a29bb4486ae47a83ce0124a170b51ff67">00049</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a29bb4486ae47a83ce0124a170b51ff67">hex0</a>,
<a name="l00050"></a><a class="code" href="classdrv__debug.html#a14cf02ea6548d1bae7a012fb5b5b3714">00050</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a14cf02ea6548d1bae7a012fb5b5b3714">hex1</a>,
<a name="l00051"></a><a class="code" href="classdrv__debug.html#a95201ed0da47b8059f4497af75f757c7">00051</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a95201ed0da47b8059f4497af75f757c7">hex2</a>,
<a name="l00052"></a><a class="code" href="classdrv__debug.html#a0d10bdcabc692b98cd821650ff11e3b1">00052</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a0d10bdcabc692b98cd821650ff11e3b1">hex3</a>,
<a name="l00053"></a><a class="code" href="classdrv__debug.html#a86293bf7d1b5f04ce39148ba97d526a9">00053</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a86293bf7d1b5f04ce39148ba97d526a9">hex4</a>,
<a name="l00054"></a><a class="code" href="classdrv__debug.html#a3c2a491bb10a7c7b9f16724f53f99930">00054</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a3c2a491bb10a7c7b9f16724f53f99930">hex5</a>,
<a name="l00055"></a><a class="code" href="classdrv__debug.html#aefbfeea8e3202f7af9e2d7ba54561fba">00055</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#aefbfeea8e3202f7af9e2d7ba54561fba">hex6</a>,
<a name="l00056"></a><a class="code" href="classdrv__debug.html#aa6a37e7b63418b1b3e51094f3f432908">00056</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#aa6a37e7b63418b1b3e51094f3f432908">hex7</a>,
<a name="l00057"></a>00057 <span class="keyword">// switches input</span>
<a name="l00058"></a><a class="code" href="classdrv__debug.html#aa62d2fc6402d3c48aec2b7b2a149c3e0">00058</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdrv__debug.html#aa62d2fc6402d3c48aec2b7b2a149c3e0">debug_sw_pc</a>,
<a name="l00059"></a><a class="code" href="classdrv__debug.html#aaffc08056af623227f58da61300c029d">00059</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdrv__debug.html#aaffc08056af623227f58da61300c029d">debug_sw_adr</a>
<a name="l00060"></a>00060 <span class="keyword">//% @}</span>
<a name="l00061"></a>00061 );
<a name="l00062"></a>00062
<a name="l00063"></a>00063 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a29bb4486ae47a83ce0124a170b51ff67">hex0</a> =
<a name="l00064"></a>00064 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00065"></a>00065 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00066"></a>00066 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00067"></a>00067 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00068"></a>00068 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00069"></a>00069 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00070"></a>00070 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00071"></a>00071 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00072"></a>00072 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00073"></a>00073 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00074"></a>00074 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00075"></a>00075 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00076"></a>00076 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00077"></a>00077 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00078"></a>00078 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00079"></a>00079 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00080"></a>00080 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a14cf02ea6548d1bae7a012fb5b5b3714">hex1</a> =
<a name="l00081"></a>00081 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00082"></a>00082 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00083"></a>00083 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00084"></a>00084 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00085"></a>00085 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00086"></a>00086 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00087"></a>00087 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00088"></a>00088 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00089"></a>00089 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00090"></a>00090 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00091"></a>00091 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00092"></a>00092 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00093"></a>00093 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00094"></a>00094 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00095"></a>00095 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00096"></a>00096 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00097"></a>00097 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a95201ed0da47b8059f4497af75f757c7">hex2</a> =
<a name="l00098"></a>00098 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00099"></a>00099 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00100"></a>00100 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00101"></a>00101 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00102"></a>00102 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00103"></a>00103 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00104"></a>00104 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00105"></a>00105 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00106"></a>00106 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00107"></a>00107 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00108"></a>00108 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00109"></a>00109 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00110"></a>00110 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00111"></a>00111 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00112"></a>00112 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00113"></a>00113 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00114"></a>00114 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a0d10bdcabc692b98cd821650ff11e3b1">hex3</a> =
<a name="l00115"></a>00115 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00116"></a>00116 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00117"></a>00117 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00118"></a>00118 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00119"></a>00119 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00120"></a>00120 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00121"></a>00121 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00122"></a>00122 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00123"></a>00123 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00124"></a>00124 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00125"></a>00125 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00126"></a>00126 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00127"></a>00127 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00128"></a>00128 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00129"></a>00129 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00130"></a>00130 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00131"></a>00131 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a86293bf7d1b5f04ce39148ba97d526a9">hex4</a> =
<a name="l00132"></a>00132 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00133"></a>00133 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00134"></a>00134 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00135"></a>00135 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00136"></a>00136 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00137"></a>00137 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00138"></a>00138 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00139"></a>00139 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00140"></a>00140 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00141"></a>00141 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00142"></a>00142 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00143"></a>00143 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00144"></a>00144 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00145"></a>00145 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00146"></a>00146 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00147"></a>00147 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00148"></a>00148 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#a3c2a491bb10a7c7b9f16724f53f99930">hex5</a> =
<a name="l00149"></a>00149 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00150"></a>00150 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00151"></a>00151 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00152"></a>00152 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00153"></a>00153 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00154"></a>00154 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00155"></a>00155 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00156"></a>00156 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00157"></a>00157 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00158"></a>00158 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00159"></a>00159 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00160"></a>00160 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00161"></a>00161 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00162"></a>00162 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00163"></a>00163 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00164"></a>00164 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00165"></a>00165 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#aefbfeea8e3202f7af9e2d7ba54561fba">hex6</a> =
<a name="l00166"></a>00166 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00167"></a>00167 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00168"></a>00168 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00169"></a>00169 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00170"></a>00170 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00171"></a>00171 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00172"></a>00172 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00173"></a>00173 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00174"></a>00174 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00175"></a>00175 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00176"></a>00176 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00177"></a>00177 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00178"></a>00178 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00179"></a>00179 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00180"></a>00180 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00181"></a>00181 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00182"></a>00182 <span class="vhdlkeyword">assign</span> <a class="code" href="classdrv__debug.html#aa6a37e7b63418b1b3e51094f3f432908">hex7</a> =
<a name="l00183"></a>00183 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
<a name="l00184"></a>00184 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
<a name="l00185"></a>00185 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
<a name="l00186"></a>00186 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
<a name="l00187"></a>00187 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
<a name="l00188"></a>00188 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
<a name="l00189"></a>00189 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
<a name="l00190"></a>00190 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
<a name="l00191"></a>00191 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
<a name="l00192"></a>00192 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
<a name="l00193"></a>00193 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
<a name="l00194"></a>00194 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
<a name="l00195"></a>00195 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
<a name="l00196"></a>00196 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
<a name="l00197"></a>00197 (<a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
<a name="l00198"></a>00198 ~<span class="vhdllogic">8'b01110001</span>;
<a name="l00199"></a><a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">00199</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a>;
<a name="l00200"></a>00200
<a name="l00201"></a><a class="code" href="classdrv__debug.html#a4d3363cafc055d3a43d966b389c9e1eb">00201</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classdrv__debug.html#a7e36153a71f34792696d16581a6d5f67">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classdrv__debug.html#acd52a7205cfc84d2188f33227e734941">reset_n</a>) <span class="vhdlkeyword">begin</span>
<a name="l00202"></a>00202 <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__debug.html#acd52a7205cfc84d2188f33227e734941">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
<a name="l00203"></a>00203 <a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a> <= <span class="vhdllogic">32'd0</span>;
<a name="l00204"></a>00204 <span class="vhdlkeyword">end</span>
<a name="l00205"></a>00205 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
<a name="l00206"></a>00206 <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__debug.html#aa62d2fc6402d3c48aec2b7b2a149c3e0">debug_sw_pc</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a> <= <a class="code" href="classdrv__debug.html#a458757362a58ddbbe763586cb38419d0">debug_pc</a>;
<a name="l00207"></a>00207 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdrv__debug.html#aaffc08056af623227f58da61300c029d">debug_sw_adr</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a> <= {<a class="code" href="classdrv__debug.html#abea03e7c35c90ebd53d600056c06cbb5">master_adr_o</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>], <span class="vhdllogic">2'b00</span> };
<a name="l00208"></a>00208 <span class="vhdlkeyword">else</span> <a class="code" href="classdrv__debug.html#a63597b1cee1d4cf7b6c83630c231baa5">display</a> <= { <a class="code" href="classdrv__debug.html#ad91c26028449d56aa73ee49500f7bce6">debug_track</a>, <span class="vhdllogic">16'd0</span>, <a class="code" href="classdrv__debug.html#a406932e72315d7f81c77d0179d3d564f">debug_syscon</a> };
<a name="l00209"></a>00209 <span class="vhdlkeyword">end</span>
<a name="l00210"></a>00210 <span class="vhdlkeyword">end</span>
<a name="l00211"></a>00211 <span class="vhdlkeyword">endmodule</span>
<a name="l00212"></a>00212
<a name="l00213"></a>00213 <span class="keyword">// ---------------- general DEBUG</span>
<a name="l00214"></a>00214 <span class="keyword">/*</span>
<a name="l00215"></a>00215 <span class="keyword">wire debug_write;</span>
<a name="l00216"></a>00216 <span class="keyword">assign debug_write = master1_cyc_o == 1'b1 && master1_stb_o == 1'b1 && master1_we_o == 1'b0 && master1_adr_o != last_addr &&</span>
<a name="l00217"></a>00217 <span class="keyword"> ({master1_adr_o[31:2], 2'b00} >= 32'h00DFF000) && ({master1_adr_o[31:2], 2'b00} <= 32'h00DFF01C);</span>
<a name="l00218"></a>00218 <span class="keyword"></span>
<a name="l00219"></a>00219 <span class="keyword">reg [11:0] debug_addr;</span>
<a name="l00220"></a>00220 <span class="keyword">reg [31:2] last_addr;</span>
<a name="l00221"></a>00221 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
<a name="l00222"></a>00222 <span class="keyword"> if(reset_n == 1'b0) last_addr <= 30'd0;</span>
<a name="l00223"></a>00223 <span class="keyword"> else last_addr <= master1_adr_o; </span>
<a name="l00224"></a>00224 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00225"></a>00225 <span class="keyword"></span>
<a name="l00226"></a>00226 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
<a name="l00227"></a>00227 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 12'd0;</span>
<a name="l00228"></a>00228 <span class="keyword"> else if(debug_write == 1'b1 //&& debug_addr < 12'd4095//) debug_addr <= debug_addr + 12'd1;</span>
<a name="l00229"></a>00229 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00230"></a>00230 <span class="keyword"></span>
<a name="l00231"></a>00231 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00232"></a>00232 <span class="keyword"> .clock0(clk_30),</span>
<a name="l00233"></a>00233 <span class="keyword"></span>
<a name="l00234"></a>00234 <span class="keyword"> .address_a(debug_addr),</span>
<a name="l00235"></a>00235 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
<a name="l00236"></a>00236 <span class="keyword"> .data_a( { 3'b0, master1_adr_o[8:2], 2'b00} ),</span>
<a name="l00237"></a>00237 <span class="keyword"> .q_a()</span>
<a name="l00238"></a>00238 <span class="keyword">);</span>
<a name="l00239"></a>00239 <span class="keyword">defparam </span>
<a name="l00240"></a>00240 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00241"></a>00241 <span class="keyword"> debug_ram_inst.width_a = 12,</span>
<a name="l00242"></a>00242 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
<a name="l00243"></a>00243 <span class="keyword"> debug_ram_inst.widthad_a = 12;</span>
<a name="l00244"></a>00244 <span class="keyword">*/</span>
<a name="l00245"></a>00245
<a name="l00246"></a>00246 <span class="keyword">/*</span>
<a name="l00247"></a>00247 <span class="keyword">// ----------------------------- copper DEBUG</span>
<a name="l00248"></a>00248 <span class="keyword">wire debug_write;</span>
<a name="l00249"></a>00249 <span class="keyword">assign debug_write = (state == S_SAVE && ACK_I == 1'b1);</span>
<a name="l00250"></a>00250 <span class="keyword"></span>
<a name="l00251"></a>00251 <span class="keyword">reg [7:0] debug_addr;</span>
<a name="l00252"></a>00252 <span class="keyword">always @(posedge CLK_I) begin</span>
<a name="l00253"></a>00253 <span class="keyword"> if(line_start == 1'b1 && line_number == 9'd0) debug_addr <= 8'd0;</span>
<a name="l00254"></a>00254 <span class="keyword"> else if(debug_write == 1'b1 && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;</span>
<a name="l00255"></a>00255 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00256"></a>00256 <span class="keyword"></span>
<a name="l00257"></a>00257 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00258"></a>00258 <span class="keyword"> .clock0(CLK_I),</span>
<a name="l00259"></a>00259 <span class="keyword"></span>
<a name="l00260"></a>00260 <span class="keyword"> .address_a(debug_addr),</span>
<a name="l00261"></a>00261 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
<a name="l00262"></a>00262 <span class="keyword"> .data_a({3'b0, line_number, ir}),</span>
<a name="l00263"></a>00263 <span class="keyword"> .q_a()</span>
<a name="l00264"></a>00264 <span class="keyword">);</span>
<a name="l00265"></a>00265 <span class="keyword">defparam </span>
<a name="l00266"></a>00266 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00267"></a>00267 <span class="keyword"> debug_ram_inst.width_a = 60,</span>
<a name="l00268"></a>00268 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=cop",</span>
<a name="l00269"></a>00269 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
<a name="l00270"></a>00270 <span class="keyword">*/</span>
<a name="l00271"></a>00271
<a name="l00272"></a>00272 <span class="keyword">//------------------------- video DEBUG</span>
<a name="l00273"></a>00273 <span class="keyword">/*</span>
<a name="l00274"></a>00274 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00275"></a>00275 <span class="keyword"> .clock0(CLK_I),</span>
<a name="l00276"></a>00276 <span class="keyword"></span>
<a name="l00277"></a>00277 <span class="keyword"> .address_a(bitplain_ram_addr),</span>
<a name="l00278"></a>00278 <span class="keyword"> .wren_a(burst_read_ready == 1'b1 && burst_read_request == 1'b1 && line_number == 9'hF4),</span>
<a name="l00279"></a>00279 <span class="keyword"> .data_a({dma_address_full, (dma_address_full[1] == 1'b0) ? burst_read_data : {even_data, burst_read_data[31:16]}, 3'b0, burst_read_enabled }),</span>
<a name="l00280"></a>00280 <span class="keyword"> .q_a()</span>
<a name="l00281"></a>00281 <span class="keyword">);</span>
<a name="l00282"></a>00282 <span class="keyword">defparam </span>
<a name="l00283"></a>00283 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00284"></a>00284 <span class="keyword"> debug_ram_inst.width_a = 68,</span>
<a name="l00285"></a>00285 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=bpl",</span>
<a name="l00286"></a>00286 <span class="keyword"> debug_ram_inst.widthad_a = 5;</span>
<a name="l00287"></a>00287 <span class="keyword">*/</span>
<a name="l00288"></a>00288 <span class="keyword">/*</span>
<a name="l00289"></a>00289 <span class="keyword">wire debug_write;</span>
<a name="l00290"></a>00290 <span class="keyword">assign debug_write = (line_number >= 9'd64 && write_ena == 1'b1 && write_address == 1'b0);</span>
<a name="l00291"></a>00291 <span class="keyword"></span>
<a name="l00292"></a>00292 <span class="keyword">reg [7:0] debug_addr;</span>
<a name="l00293"></a>00293 <span class="keyword">always @(posedge CLK_I or negedge reset_n) begin</span>
<a name="l00294"></a>00294 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 8'd0;</span>
<a name="l00295"></a>00295 <span class="keyword"> else if(debug_write == 1'b1) debug_addr <= debug_addr + 8'd1;</span>
<a name="l00296"></a>00296 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00297"></a>00297 <span class="keyword"></span>
<a name="l00298"></a>00298 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00299"></a>00299 <span class="keyword"> .clock0(CLK_I),</span>
<a name="l00300"></a>00300 <span class="keyword"></span>
<a name="l00301"></a>00301 <span class="keyword"> .address_a(debug_addr),</span>
<a name="l00302"></a>00302 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
<a name="l00303"></a>00303 <span class="keyword"> .data_a( { 3'b0, line_number, 3'b0, column_number, 2'b0, dma_state, write_sel, write_data, dma_address_full } ),</span>
<a name="l00304"></a>00304 <span class="keyword"> .q_a()</span>
<a name="l00305"></a>00305 <span class="keyword">);</span>
<a name="l00306"></a>00306 <span class="keyword">defparam </span>
<a name="l00307"></a>00307 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00308"></a>00308 <span class="keyword"> debug_ram_inst.width_a = 96,</span>
<a name="l00309"></a>00309 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
<a name="l00310"></a>00310 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
<a name="l00311"></a>00311 <span class="keyword">*/</span>
<a name="l00312"></a>00312
<a name="l00313"></a>00313 <span class="keyword">// ---------------- floppy DEBUG</span>
<a name="l00314"></a>00314 <span class="keyword">/*</span>
<a name="l00315"></a>00315 <span class="keyword">wire debug_write;</span>
<a name="l00316"></a>00316 <span class="keyword">assign debug_write = (buffer_read_cycle == 1'b1 && state != S_WRITE_TO_SD);</span>
<a name="l00317"></a>00317 <span class="keyword"></span>
<a name="l00318"></a>00318 <span class="keyword">reg [7:0] debug_addr;</span>
<a name="l00319"></a>00319 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
<a name="l00320"></a>00320 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 8'd0;</span>
<a name="l00321"></a>00321 <span class="keyword"> else if(debug_write == 1'b1 && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;</span>
<a name="l00322"></a>00322 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00323"></a>00323 <span class="keyword"></span>
<a name="l00324"></a>00324 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00325"></a>00325 <span class="keyword"> .clock0(clk_30),</span>
<a name="l00326"></a>00326 <span class="keyword"></span>
<a name="l00327"></a>00327 <span class="keyword"> .address_a(debug_addr),</span>
<a name="l00328"></a>00328 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
<a name="l00329"></a>00329 <span class="keyword"> .data_a( { mfm_decoder[11:8], dsklen, dskptr, 4'b1111 } ),</span>
<a name="l00330"></a>00330 <span class="keyword"> .q_a()</span>
<a name="l00331"></a>00331 <span class="keyword">);</span>
<a name="l00332"></a>00332 <span class="keyword">defparam </span>
<a name="l00333"></a>00333 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00334"></a>00334 <span class="keyword"> debug_ram_inst.width_a = 56,</span>
<a name="l00335"></a>00335 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=flop",</span>
<a name="l00336"></a>00336 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
<a name="l00337"></a>00337 <span class="keyword">*/</span>
<a name="l00338"></a>00338
<a name="l00339"></a>00339 <span class="keyword">//------------------------------------------------- video_priority DEBUG</span>
<a name="l00340"></a>00340 <span class="keyword">/*</span>
<a name="l00341"></a>00341 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00342"></a>00342 <span class="keyword"> .clock0(CLK_I),</span>
<a name="l00343"></a>00343 <span class="keyword"></span>
<a name="l00344"></a>00344 <span class="keyword"> .address_a(line_ram_addr),</span>
<a name="l00345"></a>00345 <span class="keyword"> .wren_a(line_ena == 1'b1 && line_number == 9'd150 && column_number >= 9'h81 &&</span>
<a name="l00346"></a>00346 <span class="keyword"> ((column_number == 9'h1C1 && line_ram_counter == 3'd1) || (column_number < 9'h1C1 && line_ram_counter == 3'd3))),</span>
<a name="l00347"></a>00347 <span class="keyword"> .data_a((column_number == 9'h1C1 && line_ram_counter == 3'd1)? { final_color_value, 24'd0 } : { line_ram_data[23:0], final_color_value }),</span>
<a name="l00348"></a>00348 <span class="keyword"> .q_a()</span>
<a name="l00349"></a>00349 <span class="keyword">);</span>
<a name="l00350"></a>00350 <span class="keyword">defparam </span>
<a name="l00351"></a>00351 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00352"></a>00352 <span class="keyword"> debug_ram_inst.width_a = 36,</span>
<a name="l00353"></a>00353 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
<a name="l00354"></a>00354 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
<a name="l00355"></a>00355 <span class="keyword">*/</span>
<a name="l00356"></a>00356
<a name="l00357"></a>00357 <span class="keyword">// ----------------------------- cia8520 DEBUG</span>
<a name="l00358"></a>00358 <span class="keyword">/*</span>
<a name="l00359"></a>00359 <span class="keyword">wire debug_write;</span>
<a name="l00360"></a>00360 <span class="keyword">assign debug_write = (last_irq_n == 1'b1 && irq_n == 1'b0);</span>
<a name="l00361"></a>00361 <span class="keyword"></span>
<a name="l00362"></a>00362 <span class="keyword">reg last_irq_n;</span>
<a name="l00363"></a>00363 <span class="keyword">always @(posedge CLK_I or negedge reset_n) begin</span>
<a name="l00364"></a>00364 <span class="keyword"> if(reset_n == 1'b0) last_irq_n <= 1'b1;</span>
<a name="l00365"></a>00365 <span class="keyword"> else last_irq_n <= irq_n;</span>
<a name="l00366"></a>00366 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00367"></a>00367 <span class="keyword"></span>
<a name="l00368"></a>00368 <span class="keyword">reg [7:0] debug_addr;</span>
<a name="l00369"></a>00369 <span class="keyword">always @(posedge CLK_I) begin</span>
<a name="l00370"></a>00370 <span class="keyword"> if(debug_write == 1'b1 && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;</span>
<a name="l00371"></a>00371 <span class="keyword"><span class="vhdlkeyword">end</span></span>
<a name="l00372"></a>00372 <span class="keyword"></span>
<a name="l00373"></a>00373 <span class="keyword">altsyncram debug_ram_inst(</span>
<a name="l00374"></a>00374 <span class="keyword"> .clock0(CLK_I),</span>
<a name="l00375"></a>00375 <span class="keyword"></span>
<a name="l00376"></a>00376 <span class="keyword"> .address_a(debug_addr),</span>
<a name="l00377"></a>00377 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
<a name="l00378"></a>00378 <span class="keyword"> .data_a( {2'b0, icr_mask, 2'b0, icr_data, last_cnt_i, cnt_i, cra, serial_latch } ),</span>
<a name="l00379"></a>00379 <span class="keyword"> .q_a()</span>
<a name="l00380"></a>00380 <span class="keyword">);</span>
<a name="l00381"></a>00381 <span class="keyword">defparam </span>
<a name="l00382"></a>00382 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
<a name="l00383"></a>00383 <span class="keyword"> debug_ram_inst.width_a = 32,</span>
<a name="l00384"></a>00384 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=cia",</span>
<a name="l00385"></a>00385 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
<a name="l00386"></a>00386 <span class="keyword">*/</span>
</pre></div></div>
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