Subversion Repositories biquad

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Project Name:  Biquad IIR Filter Core
 
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Specifications:
 
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<li>IIR filter with two poles and two zeros</<li>
<li>Data width set by user</li>
<li>Coefficient width set by user up to 16 bits</li>
<li>Wishbone interface for read and write of filter coefficient registers</li>
<li>Multiple filters can be combined to form filters with more than two poles and zeros</li><br><br><br>
 
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Description:
 
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The difference equation for the biquad filter is:<br><br>
y[n] = b10*x[n] + b11*x[n-1] + b12*x[n-2] + a11*y[n-1] + a12*y[n-2]<br><br>
This equation is implemented as shown below:
<img src="bquad_blk.gif"><br><br>
Specification in pdf format:  <a href="biquad.pdf" target=_new>biquad.pdf</a><br><br>
 
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Synthesis:
 
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Synthesized with Synopsys FPGA Express version 2000.11-FE3.5.
 
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Current Status:
 
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Verilog <a href="vsource.html" target=_new>source</a> code available.
 
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Author & Maintainer:
 
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<ul><a href="mailto:ccox@opencores.org_NOSPAM">Chuck Cox</a></ul><br>
If you use this core please let me know.
 
 
 
 
 
 
 
 
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