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----------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    5
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          694 out of   1,920   36%
    Number of Slices containing only related logic:     694 out of     694  100%
    Number of Slices containing unrelated logic:          0 out of     694    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  113 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs             6 out of 74      8%

   Number of Slices                  694 out of 1920   36%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98af6c) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
......................................
Phase 6.8 (Checksum:a92ff3) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 4717 unrouted;       REAL time: 2 secs 

Phase 2: 4442 unrouted;       REAL time: 2 secs 

Phase 3: 2150 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX0| No   |  255 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  83 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Sun Sep 24 10:26:34 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------



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deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
deleting "maindcm.v"
deleting "xaw2verilog.log"
deleting "topbox.lso"
deleting "topbox_summary.html"
deleting "topbox.syr"
deleting "topbox.prj"
deleting "topbox.sprj"
deleting "topbox.ana"
deleting "topbox.stx"
deleting "topbox.cmd_log"
deleting "topbox.ngc"
deleting "topbox.ngr"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox_summary.html"
deleting "if"
deleting " $IsCopy "
deleting ""
deleting "            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule""
deleting "         "
ERROR: error deleting "         ": no such file or directory
deleting "if"
deleting " $IsCopy "
deleting ""
deleting "            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule""
deleting "         "
ERROR: error deleting "         ": no such file or directory
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "if"
deleting " $IsCopy "
deleting ""
deleting "            Xilinx::Dpm::dpm_flowUtilsFilesToDelete "DID_File"  "$HDLModule""
deleting "         "
ERROR: error deleting "         ": no such file or directory
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
deleting "maindcm.v"
deleting "xaw2verilog.log"
deleting "topbox.lso"
deleting "topbox_summary.html"
deleting "topbox.syr"
deleting "topbox.prj"
deleting "topbox.sprj"
deleting "topbox.ana"
deleting "topbox.stx"
deleting "topbox.cmd_log"
deleting "topbox.ngc"
deleting "topbox.ngr"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox.prm"
deleting "topbox.isc"
deleting "topbox.svf"
deleting "xilinx.sys"
deleting "topbox.mcs"
deleting "topbox.exo"
deleting "topbox.hex"
deleting "topbox.tek"
deleting "topbox.dst"
deleting "topbox.dst_compressed"
deleting "topbox.mpm"
deleting "_impact.cmd"
ERROR: error deleting "_impact.cmd": permission denied
deleting "_impact.log"
ERROR: error deleting "_impact.log": permission denied
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox.prm"
deleting "topbox.isc"
deleting "topbox.svf"
deleting "xilinx.sys"
deleting "topbox.mcs"
deleting "topbox.exo"
deleting "topbox.hex"
deleting "topbox.tek"
deleting "topbox.dst"
deleting "topbox.dst_compressed"
deleting "topbox.mpm"
deleting "_impact.cmd"
ERROR: error deleting "_impact.cmd": permission denied
deleting "_impact.log"
ERROR: error deleting "_impact.log": permission denied
deleting "__projnav/maindcm_jhdparse_tcl.rsp"
deleting "maindcm.v"
deleting "xaw2verilog.log"
deleting "topbox.lso"
deleting "topbox_summary.html"
deleting "topbox.syr"
deleting "topbox.prj"
deleting "topbox.sprj"
deleting "topbox.ana"
deleting "topbox.stx"
deleting "topbox.cmd_log"
deleting "topbox.ngc"
deleting "topbox.ngr"
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox.prm"
deleting "topbox.isc"
deleting "topbox.svf"
deleting "xilinx.sys"
deleting "topbox.mcs"
deleting "topbox.exo"
deleting "topbox.hex"
deleting "topbox.tek"
deleting "topbox.dst"
deleting "topbox.dst_compressed"
deleting "topbox.mpm"
deleting "_impact.cmd"
ERROR: error deleting "_impact.cmd": permission denied
deleting "_impact.log"
ERROR: error deleting "_impact.log": permission denied
deleting "__projnav/ednTOngd_tcl.rsp"
deleting ""c:\blue71/_ngo""
deleting "topbox.ngd"
deleting "topbox_ngdbuild.nav"
deleting "topbox.bld"
deleting "tobox.ucf.untf"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
deleting "topbox_map.ngm"
deleting "__projnav/ncdTOtwr_tcl.rsp"
deleting "topbox.twr"
deleting "topbox.twx"
deleting "topbox.tsi"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "__projnav/nc1TOncd_tcl.rsp"
deleting "topbox.ncd"
deleting "topbox.par"
deleting "topbox.pad"
deleting "topbox_pad.txt"
deleting "topbox_pad.csv"
deleting "topbox.pad_txt"
deleting "topbox.dly"
deleting "reportgen.log"
deleting "topbox.xpi"
deleting "topbox.grf"
deleting "topbox.itr"
deleting "topbox_last_par.ncd"
deleting "topbox.placed_ncd_tracker"
deleting "topbox.routed_ncd_tracker"
deleting "topbox.cmd_log"
deleting "__projnav/topbox_ncdTOut_tcl.rsp"
deleting "__projnav/bitgen.rsp"
deleting "bitgen.ut"
deleting "topbox.ut"
deleting "topbox.bgn"
deleting "topbox.rbt"
deleting "topbox.ll"
deleting "topbox.msk"
deleting "topbox.drc"
deleting "topbox.nky"
deleting "topbox.bit"
deleting "topbox.bin"
deleting "topbox.isc"
deleting "topbox.cmd_log"
deleting "topbox_summary.html"
deleting "topbox_map.ncd"
deleting "topbox.ngm"
deleting "topbox.pcf"
deleting "topbox.nc1"
deleting "topbox.mrp"
deleting "topbox_map.mrp"
deleting "topbox.mdf"
deleting "topbox.cmd_log"
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Finished cleaning up project


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2verilog: Completed successfully










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop loadnow has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     611  out of   1920    31%  
 Number of Slice Flip Flops:           393  out of   3840    10%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 393   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.383ns
   Maximum combinational path delay: 14.555ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -aul -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    5
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          694 out of   1,920   36%
    Number of Slices containing only related logic:     694 out of     694  100%
    Number of Slices containing unrelated logic:          0 out of     694    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  113 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs             6 out of 74      8%

   Number of Slices                  694 out of 1920   36%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98af6c) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
......................................
Phase 6.8 (Checksum:a92ff3) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 4717 unrouted;       REAL time: 2 secs 

Phase 2: 4442 unrouted;       REAL time: 2 secs 

Phase 3: 2150 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX0| No   |  255 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  83 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Sun Sep 24 10:28:03 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
FlipFlop CPU/IR/regvalue_0 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_5 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     648  out of   1920    33%  
 Number of Slice Flip Flops:           385  out of   3840    10%  
 Number of 4 input LUTs:              1154  out of   3840    30%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 385   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.928ns (Maximum Frequency: 66.987MHz)
   Minimum input arrival time before clock: 10.934ns
   Maximum output required time after clock: 25.303ns
   Maximum combinational path delay: 14.935ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...
ERROR:NgdBuild:756 - Line 213 in 'tobox.ucf': Could not find net(s) 'CPU/cp<4>'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "tobox.ucf".

Writing NGDBUILD log file "topbox.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
FlipFlop CPU/IR/regvalue_0 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_5 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     648  out of   1920    33%  
 Number of Slice Flip Flops:           385  out of   3840    10%  
 Number of 4 input LUTs:              1154  out of   3840    30%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 385   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.928ns (Maximum Frequency: 66.987MHz)
   Minimum input arrival time before clock: 10.934ns
   Maximum output required time after clock: 25.303ns
   Maximum combinational path delay: 14.935ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...
ERROR:NgdBuild:756 - Line 213 in 'tobox.ucf': Could not find net(s) 'CPU/cp<4>'
   in the design.  To suppress this error specify the correct net name or remove
   the constraint.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file "tobox.ucf".

Writing NGDBUILD log file "topbox.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         359 out of   3,840    9%
  Number of 4 input LUTs:           1,203 out of   3,840   31%
Logic Distribution:
  Number of occupied Slices:                          714 out of   1,920   37%
    Number of Slices containing only related logic:     714 out of     714  100%
    Number of Slices containing unrelated logic:          0 out of     714    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,207 out of   3,840   31%
  Number used as logic:              1,203
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,177
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  113 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs             6 out of 74      8%

   Number of Slices                  714 out of 1920   37%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98b020) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
.......................
Phase 6.8 (Checksum:abcfab) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 4902 unrouted;       REAL time: 2 secs 

Phase 2: 4634 unrouted;       REAL time: 2 secs 

Phase 3: 2271 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX0| No   |  248 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  83 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Sun Sep 24 10:35:47 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     609  out of   1920    31%  
 Number of Slice Flip Flops:           368  out of   3840     9%  
 Number of 4 input LUTs:              1078  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 368   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.634ns (Maximum Frequency: 68.333MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.823ns
   Maximum combinational path delay: 14.545ns

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         342 out of   3,840    8%
  Number of 4 input LUTs:           1,128 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          661 out of   1,920   34%
    Number of Slices containing only related logic:     661 out of     661  100%
    Number of Slices containing unrelated logic:          0 out of     661    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,132 out of   3,840   29%
  Number used as logic:              1,128
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,594
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  114 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs             6 out of 74      8%

   Number of Slices                  661 out of 1920   34%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98ae43) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.8
..................................
Phase 6.8 (Checksum:a893f9) REAL time: 1 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 1 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 4597 unrouted;       REAL time: 2 secs 

Phase 2: 4346 unrouted;       REAL time: 2 secs 

Phase 3: 2122 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX0| No   |  231 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  82 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Sun Sep 24 10:39:12 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2verilog: Completed successfully










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     609  out of   1920    31%  
 Number of Slice Flip Flops:           368  out of   3840     9%  
 Number of 4 input LUTs:              1078  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 368   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.634ns (Maximum Frequency: 68.333MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.823ns
   Maximum combinational path delay: 14.545ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         342 out of   3,840    8%
  Number of 4 input LUTs:           1,128 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          661 out of   1,920   34%
    Number of Slices containing only related logic:     661 out of     661  100%
    Number of Slices containing unrelated logic:          0 out of     661    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,132 out of   3,840   29%
  Number used as logic:              1,128
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,594
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  113 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  661 out of 1920   34%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98ae43) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.8
..............................
Phase 4.8 (Checksum:a3e327) REAL time: 1 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 4597 unrouted;       REAL time: 2 secs 

Phase 2: 4347 unrouted;       REAL time: 2 secs 

Phase 3: 2175 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 4 secs 


Total REAL time to Router completion: 4 secs 
Total CPU time to Router completion: 4 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  231 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 4 secs 

Peak Memory Usage:  82 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Analysis completed Sun Sep 24 10:42:52 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         342 out of   3,840    8%
  Number of 4 input LUTs:           1,128 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          661 out of   1,920   34%
    Number of Slices containing only related logic:     661 out of     661  100%
    Number of Slices containing unrelated logic:          0 out of     661    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,132 out of   3,840   29%
  Number used as logic:              1,128
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,594
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  113 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  661 out of 1920   34%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98ae43) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.8
..............................
....
Phase 4.8 (Checksum:a448b3) REAL time: 5 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 7 secs 
Total CPU time to Placer completion: 7 secs 

Starting Router

Phase 1: 4597 unrouted;       REAL time: 7 secs 

Phase 2: 4348 unrouted;       REAL time: 7 secs 

Phase 3: 2125 unrouted;       REAL time: 8 secs 

Phase 4: 2125 unrouted; (0)      REAL time: 8 secs 

Phase 5: 2125 unrouted; (0)      REAL time: 8 secs 

Phase 6: 2125 unrouted; (0)      REAL time: 9 secs 

Phase 7: 0 unrouted; (0)      REAL time: 11 secs 

Phase 8: 0 unrouted; (0)      REAL time: 11 secs 


Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 11 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  231 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.442ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 39.710ns   | 12   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 12 secs 

Peak Memory Usage:  96 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 11:49:52 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop loadnow has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     611  out of   1920    31%  
 Number of Slice Flip Flops:           393  out of   3840    10%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 393   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.383ns
   Maximum combinational path delay: 14.555ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          694 out of   1,920   36%
    Number of Slices containing only related logic:     694 out of     694  100%
    Number of Slices containing unrelated logic:          0 out of     694    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  114 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  694 out of 1920   36%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98af6c) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 5 secs 

Phase 4.8
................
.....
Phase 4.8 (Checksum:a5b7b7) REAL time: 6 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 8 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 8 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 8 secs 
Total CPU time to Placer completion: 7 secs 

Starting Router

Phase 1: 4717 unrouted;       REAL time: 8 secs 

Phase 2: 4443 unrouted;       REAL time: 8 secs 

Phase 3: 2140 unrouted;       REAL time: 9 secs 

Phase 4: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 5: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 6: 2140 unrouted; (0)      REAL time: 10 secs 

Phase 7: 0 unrouted; (0)      REAL time: 11 secs 

Phase 8: 0 unrouted; (0)      REAL time: 12 secs 


Total REAL time to Router completion: 12 secs 
Total CPU time to Router completion: 11 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  255 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.474ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 37.488ns   | 6    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 13 secs 
Total CPU time to PAR completion: 12 secs 

Peak Memory Usage:  96 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 13:19:05 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d72d) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
.............................
Phase 4.4 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.8
................................................................................
.....
......................................................................................................................................................
...............
...............
Phase 6.8 (Checksum:ace7a1) REAL time: 22 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 22 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 22 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 31 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 31 secs 

Invoking physical synthesis ...

Physical synthesis completed.

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         366 out of   3,840    9%
  Number of 4 input LUTs:           1,146 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          759 out of   1,920   39%
    Number of Slices containing only related logic:     759 out of     759  100%
    Number of Slices containing unrelated logic:          0 out of     759    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,150 out of   3,840   29%
  Number used as logic:              1,146
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of Block RAMs:                1 out of      12    8%
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  83,433
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  154 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of RAMB16s                   1 out of 12      8%
   Number of Slices                  759 out of 1920   39%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 5000 unrouted;       REAL time: 4 secs 

Phase 2: 4653 unrouted;       REAL time: 4 secs 

Phase 3: 2167 unrouted;       REAL time: 5 secs 

Phase 4: 2167 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2167 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2167 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 8 secs 

Phase 8: 0 unrouted; (0)      REAL time: 8 secs 


Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 8 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  323 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.474ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 38.970ns   | 7    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 9 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 14:57:41 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          694 out of   1,920   36%
    Number of Slices containing only related logic:     694 out of     694  100%
    Number of Slices containing unrelated logic:          0 out of     694    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  114 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  694 out of 1920   36%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98af6c) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.8
................
.....
Phase 4.8 (Checksum:a5b7b7) REAL time: 5 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 8 secs 
Total CPU time to Placer completion: 7 secs 

Starting Router

Phase 1: 4717 unrouted;       REAL time: 8 secs 

Phase 2: 4443 unrouted;       REAL time: 8 secs 

Phase 3: 2140 unrouted;       REAL time: 8 secs 

Phase 4: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 5: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 6: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 7: 0 unrouted; (0)      REAL time: 11 secs 

Phase 8: 0 unrouted; (0)      REAL time: 11 secs 


Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 11 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  255 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.474ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 37.488ns   | 6    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 12 secs 

Peak Memory Usage:  96 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 15:14:45 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         364 out of   3,840    9%
  Number of 4 input LUTs:           1,119 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          687 out of   1,920   35%
    Number of Slices containing only related logic:     687 out of     687  100%
    Number of Slices containing unrelated logic:          0 out of     687    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,123 out of   3,840   29%
  Number used as logic:              1,119
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of Block RAMs:                3 out of      12   25%
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  214,327
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  114 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of RAMB16s                   3 out of 12     25%
   Number of Slices                  687 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98b209) REAL time: 6 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 8 secs 

Phase 4.8
........................................
....
Phase 4.8 (Checksum:a51b43) REAL time: 10 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 10 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 12 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 12 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 12 secs 
Total CPU time to Placer completion: 8 secs 

Starting Router

Phase 1: 4722 unrouted;       REAL time: 12 secs 

Phase 2: 4441 unrouted;       REAL time: 13 secs 

Phase 3: 2115 unrouted;       REAL time: 13 secs 

Phase 4: 2115 unrouted; (0)      REAL time: 14 secs 

Phase 5: 2115 unrouted; (0)      REAL time: 14 secs 

Phase 6: 2115 unrouted; (0)      REAL time: 14 secs 

Phase 7: 0 unrouted; (0)      REAL time: 16 secs 

Phase 8: 0 unrouted; (0)      REAL time: 16 secs 


Total REAL time to Router completion: 17 secs 
Total CPU time to Router completion: 12 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  255 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.026ns   | 8    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 38.558ns   | 8    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 18 secs 
Total CPU time to PAR completion: 13 secs 

Peak Memory Usage:  96 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 17:16:18 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          694 out of   1,920   36%
    Number of Slices containing only related logic:     694 out of     694  100%
    Number of Slices containing unrelated logic:          0 out of     694    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  114 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  694 out of 1920   36%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98af6c) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 4 secs 

Phase 4.8
................
.....
Phase 4.8 (Checksum:a5b7b7) REAL time: 5 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 7 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 7 secs 

Writing design to file topbox.ncd


Total REAL time to Placer completion: 7 secs 
Total CPU time to Placer completion: 7 secs 

Starting Router

Phase 1: 4717 unrouted;       REAL time: 7 secs 

Phase 2: 4443 unrouted;       REAL time: 7 secs 

Phase 3: 2140 unrouted;       REAL time: 8 secs 

Phase 4: 2140 unrouted; (0)      REAL time: 8 secs 

Phase 5: 2140 unrouted; (0)      REAL time: 8 secs 

Phase 6: 2140 unrouted; (0)      REAL time: 9 secs 

Phase 7: 0 unrouted; (0)      REAL time: 10 secs 

Phase 8: 0 unrouted; (0)      REAL time: 11 secs 


Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 11 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX3| No   |  255 |  0.042     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.474ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 37.488ns   | 6    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 12 secs 

Peak Memory Usage:  96 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 17:28:05 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.4
..............
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.....................
........
.........................
...............
...............
Phase 6.8 (Checksum:aa8209) REAL time: 9 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 9 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 18 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 18 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          691 out of   1,920   35%
    Number of Slices containing only related logic:     691 out of     691  100%
    Number of Slices containing unrelated logic:          0 out of     691    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  691 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard (set by user)
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4863 unrouted;       REAL time: 4 secs 

Phase 2: 4537 unrouted;       REAL time: 4 secs 

Phase 3: 2179 unrouted;       REAL time: 5 secs 

Phase 4: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 6: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (0)      REAL time: 8 secs 

Phase 8: 0 unrouted; (0)      REAL time: 8 secs 


Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 9 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  307 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 36.056ns   | 8    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 39.230ns   | 12   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 17:30:24 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  691 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4863 unrouted;       REAL time: 4 secs 

Phase 2: 4537 unrouted;       REAL time: 4 secs 

Phase 3: 2179 unrouted;       REAL time: 5 secs 

Phase 4: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 6: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (0)      REAL time: 8 secs 

Phase 8: 0 unrouted; (0)      REAL time: 9 secs 


Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 9 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  307 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 36.056ns   | 8    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 39.230ns   | 12   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 18:50:32 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2verilog: Completed successfully










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  5" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 40000000
        BAUD = 9600
        CLK_DIV = 130
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop loadnow has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     611  out of   1920    31%  
 Number of Slice Flip Flops:           393  out of   3840    10%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 393   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 16.248ns (Maximum Frequency: 61.546MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.383ns
   Maximum combinational path delay: 14.555ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.800000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.800000 PHASE +
12.500000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d16f) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
................................
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
..................................
.......
.................................................
....................................
...............
Phase 6.8 (Checksum:185cdc0) REAL time: 13 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 13 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 13 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 37 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 37 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,128 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          634 out of   1,920   33%
    Number of Slices containing only related logic:     634 out of     634  100%
    Number of Slices containing unrelated logic:          0 out of     634    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,128
  Number used as a route-thru:           7
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,797
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  134 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  634 out of 1920   33%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4858 unrouted;       REAL time: 4 secs 

Phase 2: 4533 unrouted;       REAL time: 4 secs 

Phase 3: 2287 unrouted;       REAL time: 5 secs 

Phase 4: 2287 unrouted; (43949)      REAL time: 5 secs 

Phase 5: 2491 unrouted; (19206)      REAL time: 6 secs 

Phase 6: 2531 unrouted; (18488)      REAL time: 7 secs 

Phase 7: 0 unrouted; (54873)      REAL time: 39 secs 

Phase 8: 0 unrouted; (54873)      REAL time: 40 secs 

Phase 9: 0 unrouted; (47807)      REAL time: 2 mins 12 secs 

Phase 10: 0 unrouted; (47807)      REAL time: 2 mins 53 secs 


Total REAL time to Router completion: 2 mins 54 secs 
Total CPU time to Router completion: 2 mins 53 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  305 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 47807

WARNING:Par:62 - Timing constraints have not been met.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 50 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
* TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 25.000ns   | 26.994ns   | 7    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.8 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
* TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 25.000ns   | 29.060ns   | 11   
  _wclk" TS_clkin * 0.8 PHASE 12.5 ns       |            |            |      
     HIGH 50%                               |            |            |      
--------------------------------------------------------------------------------


2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 mins 55 secs 
Total CPU time to PAR completion: 2 mins 53 secs 

Peak Memory Usage:  100 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - 82 errors found.

Number of error messages: 0
Number of warning messages: 5
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 25000 ps
   (40.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 22:15:06 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.800000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.800000 PHASE +
15.625000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.4
................................
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
........................
......
........................................
...............
...............
Phase 6.8 (Checksum:c19e1b) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 23 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 23 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,128 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          662 out of   1,920   34%
    Number of Slices containing only related logic:     662 out of     662  100%
    Number of Slices containing unrelated logic:          0 out of     662    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,128
  Number used as a route-thru:           7
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,797
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  662 out of 1920   34%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4870 unrouted;       REAL time: 4 secs 

Phase 2: 4541 unrouted;       REAL time: 4 secs 

Phase 3: 2229 unrouted;       REAL time: 5 secs 

Phase 4: 2229 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2229 unrouted; (0)      REAL time: 5 secs 

Phase 6: 2229 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (1830)      REAL time: 19 secs 

Phase 8: 0 unrouted; (1830)      REAL time: 20 secs 

Phase 9: 0 unrouted; (0)      REAL time: 22 secs 

Phase 10: 0 unrouted; (0)      REAL time: 22 secs 


Total REAL time to Router completion: 22 secs 
Total CPU time to Router completion: 22 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  310 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 40 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 31.250ns   | 31.234ns   | 8    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.8 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 31.250ns   | 31.236ns   | 10   
  _wclk" TS_clkin * 0.8 PHASE 15.625 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 23 secs 
Total CPU time to PAR completion: 23 secs 

Peak Memory Usage:  99 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 31250 ps
   (32.00 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 22:18:33 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "View HDL Source".

xaw2verilog: Completed successfully










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
FlipFlop CPU/IR/regvalue_0 has been replicated 3 time(s)
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_12 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_13 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_14 has been replicated 2 time(s)
FlipFlop CPU/IR/regvalue_15 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_4 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_6 has been replicated 1 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 4 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop loadnow has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     611  out of   1920    31%  
 Number of Slice Flip Flops:           393  out of   3840    10%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 393   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 14.217ns (Maximum Frequency: 70.338MHz)
   Minimum input arrival time before clock: 10.576ns
   Maximum output required time after clock: 24.383ns
   Maximum combinational path delay: 14.555ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d16f) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 2 secs 

Phase 4.4
..............
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.....................
........
.........................
...............
...............
Phase 6.8 (Checksum:aa8209) REAL time: 9 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 9 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 9 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 18 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 18 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         367 out of   3,840    9%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          691 out of   1,920   35%
    Number of Slices containing only related logic:     691 out of     691  100%
    Number of Slices containing unrelated logic:          0 out of     691    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  17,815
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  691 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4863 unrouted;       REAL time: 4 secs 

Phase 2: 4537 unrouted;       REAL time: 4 secs 

Phase 3: 2179 unrouted;       REAL time: 5 secs 

Phase 4: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 6: 2179 unrouted; (0)      REAL time: 5 secs 

Phase 7: 0 unrouted; (0)      REAL time: 8 secs 

Phase 8: 0 unrouted; (0)      REAL time: 9 secs 


Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 9 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  307 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 36.056ns   | 8    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 39.230ns   | 12   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sun Sep 24 22:22:30 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 2 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
ERROR:HDLCompilers:26 - "top.v" line 75 unexpected token: 'writeflag'
ERROR:HDLCompilers:28 - "top.v" line 100 'writeflag' has not been declared
ERROR:HDLCompilers:28 - "top.v" line 107 'writeflag' has not been declared
ERROR:HDLCompilers:28 - "top.v" line 114 'writeflag' has not been declared
ERROR:HDLCompilers:28 - "top.v" line 115 'writecf' has not been declared
ERROR:HDLCompilers:28 - "top.v" line 230 'writecf' has not been declared
ERROR:HDLCompilers:28 - "top.v" line 333 'writeflag' has not been declared
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
Analysis of file <"topbox.prj"> failed.
--> 

Total memory usage is 75092 kilobytes

Number of errors   :    7 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_108>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 29.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV35_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV35_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV23 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opframe121 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV8_SW0_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW5 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opframe14 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_2.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW4 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW1_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW0_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW4_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker201_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     615  out of   1920    32%  
 Number of Slice Flip Flops:           436  out of   3840    11%  
 Number of 4 input LUTs:              1084  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 436   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.600ns (Maximum Frequency: 73.531MHz)
   Minimum input arrival time before clock: 11.144ns
   Maximum output required time after clock: 23.245ns
   Maximum combinational path delay: 15.352ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d6b6) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
...............
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
.......................
.......
................................
...............
...............
Phase 6.8 (Checksum:aab26f) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 19 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 19 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         410 out of   3,840   10%
  Number of 4 input LUTs:           1,134 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          677 out of   1,920   35%
    Number of Slices containing only related logic:     677 out of     677  100%
    Number of Slices containing unrelated logic:          0 out of     677    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,138 out of   3,840   29%
  Number used as logic:              1,134
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,168
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  134 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  677 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4894 unrouted;       REAL time: 4 secs 

Phase 2: 4536 unrouted;       REAL time: 4 secs 

Phase 3: 2116 unrouted;       REAL time: 5 secs 

Phase 4: 2116 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2116 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2116 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 9 secs 

Phase 8: 0 unrouted; (0)      REAL time: 10 secs 


Total REAL time to Router completion: 10 secs 
Total CPU time to Router completion: 10 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  338 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 28.312ns   | 6    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 40.798ns   | 9    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 11 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Fri Sep 29 19:25:05 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     615  out of   1920    32%  
 Number of Slice Flip Flops:           433  out of   3840    11%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 433   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.483ns (Maximum Frequency: 74.169MHz)
   Minimum input arrival time before clock: 11.144ns
   Maximum output required time after clock: 23.107ns
   Maximum combinational path delay: 15.256ns

=========================================================================





Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d694) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
..............
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
........................
.......
..................
...............
...............
Phase 6.8 (Checksum:ab4095) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         407 out of   3,840   10%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          684 out of   1,920   35%
    Number of Slices containing only related logic:     684 out of     684  100%
    Number of Slices containing unrelated logic:          0 out of     684    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,123
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  684 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4897 unrouted;       REAL time: 4 secs 

Phase 2: 4533 unrouted;       REAL time: 4 secs 

Phase 3: 2191 unrouted;       REAL time: 5 secs 

Phase 4: 2191 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2191 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2191 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 9 secs 

Phase 8: 0 unrouted; (0)      REAL time: 10 secs 


Total REAL time to Router completion: 10 secs 
Total CPU time to Router completion: 10 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  344 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 24.924ns   | 4    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 38.312ns   | 10   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 11 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 00:33:08 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/F1_FRB has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/counter_0 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_1 has been replicated 3 time(s)
FlipFlop CPU/ctl/sim/counter_2 has been replicated 3 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     615  out of   1920    32%  
 Number of Slice Flip Flops:           433  out of   3840    11%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 433   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.483ns (Maximum Frequency: 74.169MHz)
   Minimum input arrival time before clock: 11.144ns
   Maximum output required time after clock: 23.107ns
   Maximum combinational path delay: 15.256ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d694) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
..............
Phase 4.4 (Checksum:26259fc) REAL time: 4 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 4 secs 

Phase 6.8
........................
.......
..................
...............
...............
Phase 6.8 (Checksum:ab4095) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         407 out of   3,840   10%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          684 out of   1,920   35%
    Number of Slices containing only related logic:     684 out of     684  100%
    Number of Slices containing unrelated logic:          0 out of     684    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,123
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  684 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4897 unrouted;       REAL time: 5 secs 

Phase 2: 4533 unrouted;       REAL time: 5 secs 

Phase 3: 2191 unrouted;       REAL time: 5 secs 

Phase 4: 2191 unrouted; (0)      REAL time: 6 secs 

Phase 5: 2191 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2191 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 9 secs 

Phase 8: 0 unrouted; (0)      REAL time: 10 secs 


Total REAL time to Router completion: 10 secs 
Total CPU time to Router completion: 10 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  344 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 23.930ns   | 5    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 40.472ns   | 9    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 11 secs 

Peak Memory Usage:  92 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 20:03:53 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
ERROR:Xst:899 - "control.v" line 48: The logic for <sw2bus> does not match a known FF or Latch template.
ERROR:Xst:899 - "control.v" line 46: The logic for <loadpc1> does not match a known FF or Latch template.
 
Found 2 error(s). Aborting synthesis.
--> 

Total memory usage is 80468 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
ERROR:Xst:899 - "control.v" line 48: The logic for <sw2bus> does not match a known FF or Latch template.
ERROR:Xst:899 - "control.v" line 46: The logic for <loadpc1> does not match a known FF or Latch template.
 
Found 2 error(s). Aborting synthesis.
--> 

Total memory usage is 80468 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
ERROR:HDLCompilers:28 - "control.v" line 67 'lodpc1' has not been declared
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
Analysis of file <"topbox.prj"> failed.
--> 

Total memory usage is 75092 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 13
 1-bit 4-to-1 multiplexer          : 10
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     616  out of   1920    32%  
 Number of Slice Flip Flops:           436  out of   3840    11%  
 Number of 4 input LUTs:              1080  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 436   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
   Minimum input arrival time before clock: 10.967ns
   Maximum output required time after clock: 23.172ns
   Maximum combinational path delay: 15.112ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d1df) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
.................
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
............................
..............
..........................
...............
...............
Phase 6.8 (Checksum:abc08d) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         410 out of   3,840   10%
  Number of 4 input LUTs:           1,130 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          654 out of   1,920   34%
    Number of Slices containing only related logic:     654 out of     654  100%
    Number of Slices containing unrelated logic:          0 out of     654    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,134 out of   3,840   29%
  Number used as logic:              1,130
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,138
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  654 out of 1920   34%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4861 unrouted;       REAL time: 4 secs 

Phase 2: 4524 unrouted;       REAL time: 4 secs 

Phase 3: 2173 unrouted;       REAL time: 5 secs 

Phase 4: 2173 unrouted; (0)      REAL time: 5 secs 

Phase 5: 2173 unrouted; (0)      REAL time: 5 secs 

Phase 6: 2173 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 9 secs 

Phase 8: 0 unrouted; (0)      REAL time: 10 secs 


Total REAL time to Router completion: 10 secs 
Total CPU time to Router completion: 10 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  317 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 26.908ns   | 6    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 38.772ns   | 9    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 12 secs 
Total CPU time to PAR completion: 11 secs 

Peak Memory Usage:  93 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 20:20:07 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0007>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   2 Multiplexer(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 15
 1-bit 4-to-1 multiplexer          : 12
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/ctl/sim/_n00131 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Forward register balancing over CPU/ctl/sim/_n00161 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/_n00121_FRB has been replicated 7 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     617  out of   1920    32%  
 Number of Slice Flip Flops:           436  out of   3840    11%  
 Number of 4 input LUTs:              1083  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 436   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.516ns (Maximum Frequency: 73.984MHz)
   Minimum input arrival time before clock: 10.967ns
   Maximum output required time after clock: 23.076ns
   Maximum combinational path delay: 15.112ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d1ef) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
......................
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.......................................
......................
........................................
................
...............
Phase 6.8 (Checksum:ac1e2f) REAL time: 11 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         410 out of   3,840   10%
  Number of 4 input LUTs:           1,133 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          677 out of   1,920   35%
    Number of Slices containing only related logic:     677 out of     677  100%
    Number of Slices containing unrelated logic:          0 out of     677    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,137 out of   3,840   29%
  Number used as logic:              1,133
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,156
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  677 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4958 unrouted;       REAL time: 4 secs 

Phase 2: 4588 unrouted;       REAL time: 4 secs 

Phase 3: 2217 unrouted;       REAL time: 5 secs 

Phase 4: 2217 unrouted; (0)      REAL time: 6 secs 

Phase 5: 2217 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2217 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 13 secs 

Phase 8: 0 unrouted; (0)      REAL time: 14 secs 


Total REAL time to Router completion: 14 secs 
Total CPU time to Router completion: 14 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  350 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 31.382ns   | 6    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 40.278ns   | 11   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 15 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  95 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 20:24:47 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 9600
        CLK_DIV = 113
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 13
 1-bit 4-to-1 multiplexer          : 10
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     617  out of   1920    32%  
 Number of Slice Flip Flops:           436  out of   3840    11%  
 Number of 4 input LUTs:              1081  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 436   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
   Minimum input arrival time before clock: 10.967ns
   Maximum output required time after clock: 23.172ns
   Maximum combinational path delay: 15.112ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d1df) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
...............
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
........................
.......
..........................
...............
...............
Phase 6.8 (Checksum:ac06bf) REAL time: 10 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 10 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 10 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 20 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 20 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         410 out of   3,840   10%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          674 out of   1,920   35%
    Number of Slices containing only related logic:     674 out of     674  100%
    Number of Slices containing unrelated logic:          0 out of     674    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,135 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           4
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,144
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  674 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router

Phase 1: 4917 unrouted;       REAL time: 4 secs 

Phase 2: 4563 unrouted;       REAL time: 4 secs 

Phase 3: 2229 unrouted;       REAL time: 5 secs 

Phase 4: 2229 unrouted; (0)      REAL time: 6 secs 

Phase 5: 2229 unrouted; (0)      REAL time: 6 secs 

Phase 6: 2229 unrouted; (0)      REAL time: 6 secs 

Phase 7: 0 unrouted; (0)      REAL time: 13 secs 

Phase 8: 0 unrouted; (0)      REAL time: 13 secs 


Total REAL time to Router completion: 14 secs 
Total CPU time to Router completion: 14 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  335 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 30.346ns   | 6    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 39.146ns   | 9    
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 15 secs 
Total CPU time to PAR completion: 15 secs 

Peak Memory Usage:  94 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 20:38:13 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "io.v"
Module <DisplayHex> compiled
Module <Debouncer> compiled
Compiling verilog file "FrontPanel.v"
Module <FrontPanel> compiled
Compiling verilog file "misc.v"
Module <constant> compiled
Module <ffff> compiled
Module <zero> compiled
Module <one> compiled
Module <register> compiled
Module <aregister> compiled
Compiling verilog file "alu.v"
Module <alu> compiled
Compiling verilog file "switchsync.v"
Module <switchsync> compiled
Compiling verilog file "jkff.v"
Module <jkff> compiled
Compiling verilog file "control.v"
Module <controlclk> compiled
Module <control> compiled
Compiling verilog file "maindcm.v"
Module <maindcm> compiled
Compiling verilog file "idecode.v"
Module <idecode> compiled
Compiling verilog file "top.v"
Module <blue> compiled
Compiling verilog file "rcvr.v"
Module <rcvr> compiled
Compiling verilog file "txmit.v"
Module <txmit> compiled
Compiling verilog file "uart.v"
Module <uart> compiled
Compiling verilog file "topbox.v"
Module <topbox> compiled
No errors in compilation
Analysis of file <"topbox.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <topbox>.
Module <topbox> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <topbox>.
Analyzing module <FrontPanel>.
Module <FrontPanel> is correct for synthesis.
 
Analyzing module <DisplayHex>.
        pClockFrequency = 50
        pRefreshFrequency = 100
        pUpperLimit = 125000
        pDividerCounterBits = 24
Module <DisplayHex> is correct for synthesis.
 
Analyzing module <Debouncer>.
        pInitialValue = 0
        pTimerWidth = 19
        pInitialTimerValue = 500000
Module <Debouncer> is correct for synthesis.
 
Analyzing module <blue>.
Module <blue> is correct for synthesis.
 
Analyzing module <register>.
        SIZE = 16
Module <register> is correct for synthesis.
 
Analyzing module <aregister>.
Module <aregister> is correct for synthesis.
 
Analyzing module <register_1>.
        SIZE = 12
Module <register_1> is correct for synthesis.
 
Analyzing module <one>.
Module <one> is correct for synthesis.
 
Analyzing module <constant>.
        VALUE = <u>0000000000000001
Module <constant> is correct for synthesis.
 
Analyzing module <ffff>.
Module <ffff> is correct for synthesis.
 
Analyzing module <constant_1>.
        VALUE = <u>1111111111111111
Module <constant_1> is correct for synthesis.
 
Analyzing module <zero>.
Module <zero> is correct for synthesis.
 
Analyzing module <constant_2>.
        VALUE = <u>0000000000000000
Module <constant_2> is correct for synthesis.
 
Analyzing module <alu>.
Module <alu> is correct for synthesis.
 
Analyzing module <control>.
Module <control> is correct for synthesis.
 
Analyzing module <controlclk>.
WARNING:Xst:854 - "control.v" line 20: Ignored initial statement.
Module <controlclk> is correct for synthesis.
 
Analyzing module <switchsync>.
WARNING:Xst:854 - "switchsync.v" line 9: Ignored initial statement.
WARNING:Xst:854 - "switchsync.v" line 10: Ignored initial statement.
Module <switchsync> is correct for synthesis.
 
Analyzing module <jkff>.
Module <jkff> is correct for synthesis.
 
Analyzing module <maindcm>.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKDV_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_DIVIDE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKFX_MULTIPLY> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_DIVIDE_BY_2> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKIN_PERIOD> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLKOUT_PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <CLK_FEEDBACK> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DESKEW_ADJUST> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DFS_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DLL_FREQUENCY_MODE> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <DUTY_CYCLE_CORRECTION> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <FACTORY_JF> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <PHASE_SHIFT> of instance <DCM_INST> set by attribute.
WARNING:Xst:2185 - "maindcm.v" line 57: Possible simulation mismatch on property <STARTUP_WAIT> of instance <DCM_INST> set by attribute.
Module <maindcm> is correct for synthesis.
 
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <maindcm>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "USELOWSKEWLINES =  " for signal <CLKFX180_OUT> in unit <maindcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_DIVIDE =  10" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKFX_MULTIPLY =  7" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <maindcm>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <maindcm>.
Analyzing module <idecode>.
Module <idecode> is correct for synthesis.
 
Analyzing module <uart>.
        XTAL_CLK = 35000000
        BAUD = 19200
        CLK_DIV = 56
        CW = 8
Module <uart> is correct for synthesis.
 
Analyzing module <rcvr>.
Module <rcvr> is correct for synthesis.
 
Analyzing module <txmit>.
Module <txmit> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <txmit>.
    Related source file is "txmit.v".
    Found 1-bit register for signal <tbre>.
    Found 1-bit register for signal <tsre>.
    Found 1-bit register for signal <sdo>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0021>.
    Found 4-bit comparator less for signal <$n0030> created at line 81.
    Found 4-bit comparator greater for signal <$n0031> created at line 81.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit up counter for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_sent>.
    Found 8-bit register for signal <tbr>.
    Found 8-bit register for signal <tsr>.
    Summary:
        inferred   2 Counter(s).
        inferred  21 D-type flip-flop(s).
        inferred   2 Comparator(s).
        inferred   1 Multiplexer(s).
Unit <txmit> synthesized.


Synthesizing Unit <rcvr>.
    Related source file is "rcvr.v".
WARNING:Xst:646 - Signal <rsr<0>> is assigned but never used.
    Found 1-bit register for signal <overrun_error>.
    Found 1-bit register for signal <data_ready>.
    Found 1-bit register for signal <framing_error>.
    Found 8-bit tristate buffer for signal <dout>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 4-bit adder for signal <$n0012> created at line 83.
    Found 4-bit comparator greater for signal <$n0019> created at line 112.
    Found 1-bit register for signal <clk1x_enable>.
    Found 1-bit register for signal <clk1xe>.
    Found 4-bit register for signal <clkdiv>.
    Found 4-bit up counter for signal <no_bits_rcvd>.
    Found 8-bit register for signal <rbr>.
    Found 7-bit register for signal <rsr<7:1>>.
    Found 1-bit register for signal <rxd1>.
    Found 1-bit register for signal <rxd2>.
    Summary:
        inferred   1 Counter(s).
        inferred  26 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   1 Comparator(s).
        inferred   1 Multiplexer(s).
        inferred   8 Tristate(s).
Unit <rcvr> synthesized.


Synthesizing Unit <jkff>.
    Related source file is "jkff.v".
    Found 1-bit register for signal <q>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0000> created at line 26.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <jkff> synthesized.


Synthesizing Unit <switchsync>.
    Related source file is "switchsync.v".
    Found 1-bit register for signal <q>.
    Found 1-bit register for signal <s0>.
    Summary:
        inferred   2 D-type flip-flop(s).
Unit <switchsync> synthesized.


Synthesizing Unit <maindcm>.
    Related source file is "maindcm.v".
Unit <maindcm> synthesized.


Synthesizing Unit <controlclk>.
    Related source file is "control.v".
    Found 1-bit register for signal <sw2bus>.
    Found 1-bit register for signal <loadpc1>.
    Found 3-bit up counter for signal <counter>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
Unit <controlclk> synthesized.


Synthesizing Unit <constant_2>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_2> synthesized.


Synthesizing Unit <constant_1>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant_1> synthesized.


Synthesizing Unit <constant>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Summary:
        inferred  16 Tristate(s).
Unit <constant> synthesized.


Synthesizing Unit <register_1>.
    Related source file is "misc.v".
WARNING:Xst:647 - Input <din<15:12>> is never used.
    Found 16-bit tristate buffer for signal <dout>.
    Found 12-bit register for signal <regvalue>.
    Summary:
        inferred  12 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register_1> synthesized.


Synthesizing Unit <idecode>.
    Related source file is "idecode.v".
Unit <idecode> synthesized.


Synthesizing Unit <control>.
    Related source file is "control.v".
Unit <control> synthesized.


Synthesizing Unit <alu>.
    Related source file is "alu.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 17-bit subtractor for signal <$AUX_109>.
    Found 16-bit adder carry out for signal <$n0000>.
    Found 1-bit xor2 for signal <$n0042> created at line 6.
    Found 1-bit xor2 for signal <$n0043> created at line 6.
    Found 16-bit xor2 for signal <$n0046> created at line 31.
    Summary:
        inferred   2 Adder/Subtractor(s).
        inferred  16 Tristate(s).
Unit <alu> synthesized.


Synthesizing Unit <zero>.
    Related source file is "misc.v".
Unit <zero> synthesized.


Synthesizing Unit <ffff>.
    Related source file is "misc.v".
Unit <ffff> synthesized.


Synthesizing Unit <one>.
    Related source file is "misc.v".
Unit <one> synthesized.


Synthesizing Unit <aregister>.
    Related source file is "misc.v".
Unit <aregister> synthesized.


Synthesizing Unit <register>.
    Related source file is "misc.v".
    Found 16-bit tristate buffer for signal <dout>.
    Found 16-bit register for signal <regvalue>.
    Summary:
        inferred  16 D-type flip-flop(s).
        inferred  16 Tristate(s).
Unit <register> synthesized.


Synthesizing Unit <Debouncer>.
    Related source file is "io.v".
    Found 1-bit register for signal <oPulseOnRisingEdge>.
    Found 1-bit register for signal <oDebounced>.
    Found 1-bit register for signal <oPulseOnFallingEdge>.
    Found 1-bit register for signal <rBouncy_Syncd>.
    Found 1-bit register for signal <rInitializeTimer>.
    Found 1-bit register for signal <rSaveInput>.
    Found 19-bit down counter for signal <rTimer>.
    Found 1-bit register for signal <rWaitForTimer>.
    Found 1-bit xor2 for signal <wTransitionDetected>.
    Summary:
        inferred   1 Counter(s).
        inferred   7 D-type flip-flop(s).
Unit <Debouncer> synthesized.


Synthesizing Unit <DisplayHex>.
    Related source file is "io.v".
    Found 16x7-bit ROM for signal <$n0005>.
    Found 1-bit register for signal <oDigitRight>.
    Found 1-bit register for signal <oSegmentDP>.
    Found 1-bit register for signal <oSegmentA>.
    Found 1-bit register for signal <oSegmentB>.
    Found 1-bit register for signal <oSegmentC>.
    Found 1-bit register for signal <oSegmentD>.
    Found 1-bit register for signal <oSegmentE>.
    Found 1-bit register for signal <oSegmentF>.
    Found 1-bit register for signal <oSegmentG>.
    Found 1-bit register for signal <oDigitMiddleLeft>.
    Found 1-bit register for signal <oDigitMiddleRight>.
    Found 1-bit register for signal <oDigitLeft>.
    Found 24-bit up counter for signal <rCycles>.
    Found 1-of-4 decoder for signal <rDigit>.
    Found 2-bit down counter for signal <rDigitSelect>.
    Found 8-bit 4-to-1 multiplexer for signal <rNybble>.
    Found 1-bit 4-to-1 multiplexer for signal <wDecimalPoint>.
    Summary:
        inferred   1 ROM(s).
        inferred   2 Counter(s).
        inferred  12 D-type flip-flop(s).
        inferred   9 Multiplexer(s).
        inferred   1 Decoder(s).
Unit <DisplayHex> synthesized.


Synthesizing Unit <uart>.
    Related source file is "uart.v".
    Found 1-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 1-bit register for signal <baud_clk>.
    Found 8-bit up counter for signal <clk_div>.
    Found 1-bit register for signal <clke>.
    Summary:
        inferred   1 Counter(s).
        inferred   2 D-type flip-flop(s).
        inferred   1 Multiplexer(s).
Unit <uart> synthesized.


Synthesizing Unit <blue>.
    Related source file is "top.v".
WARNING:Xst:1780 - Signal <mabus<15:12>> is never used or assigned.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit register for signal <Q>.
    Found 12-bit adder carry out for signal <$n0015> created at line 197.
    Found 16-bit tristate buffer for signal <bus>.
    Found 1-bit register for signal <cflag>.
    Found 1-bit register for signal <oflag>.
    Found 1-bit register for signal <zflag>.
    Summary:
        inferred   4 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred  96 Tristate(s).
Unit <blue> synthesized.


Synthesizing Unit <FrontPanel>.
    Related source file is "FrontPanel.v".
WARNING:Xst:1780 - Signal <startstop> is never used or assigned.
    Found finite state machine <FSM_0> for signal <inselect>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 6                                              |
    | Inputs             | 0                                              |
    | Outputs            | 12                                             |
    | Clock              | clockin (rising_edge)                          |
    | Clock enable       | select (positive)                              |
    | Reset              | clear (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <ledbus>.
    Found 4-bit register for signal <points>.
    Found 16-bit register for signal <switches>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred  16 D-type flip-flop(s).
        inferred  16 Multiplexer(s).
Unit <FrontPanel> synthesized.


Synthesizing Unit <topbox>.
    Related source file is "topbox.v".
WARNING:Xst:646 - Signal <step> is assigned but never used.
    Found 16-bit tristate buffer for signal <xmdata>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0006>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0008>.
    Found 4-bit 4-to-1 multiplexer for signal <$n0009>.
    Found 4-bit adder for signal <$n0012> created at line 75.
    Found 4-bit register for signal <loaddelay>.
    Found 1-bit register for signal <loadlow>.
    Found 1-bit register for signal <loadnow>.
    Found 16-bit register for signal <swregx>.
    Summary:
        inferred  22 D-type flip-flop(s).
        inferred   1 Adder/Subtractor(s).
        inferred   6 Multiplexer(s).
        inferred  48 Tristate(s).
Unit <topbox> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <inselect[1:6]> with speed1 encoding.
--------------------
 State  | Encoding
--------------------
 000001 | 100000
 000010 | 010000
 000100 | 001000
 001000 | 000100
 010000 | 000010
 100000 | 000001
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 5
 12-bit adder carry out            : 1
 16-bit adder carry out            : 1
 17-bit subtractor                 : 1
 4-bit adder                       : 2
# Counters                         : 10
 19-bit down counter               : 3
 2-bit down counter                : 1
 24-bit up counter                 : 1
 3-bit up counter                  : 1
 4-bit up counter                  : 3
 8-bit up counter                  : 1
# Registers                        : 138
 1-bit register                    : 125
 12-bit register                   : 4
 16-bit register                   : 4
 4-bit register                    : 3
 8-bit register                    : 2
# Comparators                      : 3
 4-bit comparator greater          : 2
 4-bit comparator less             : 1
# Multiplexers                     : 13
 1-bit 4-to-1 multiplexer          : 10
 16-bit 4-to-1 multiplexer         : 1
 4-bit 4-to-1 multiplexer          : 1
 8-bit 4-to-1 multiplexer          : 1
# Decoders                         : 1
 1-of-4 decoder                    : 1
# Tristates                        : 97
 1-bit tristate buffer             : 80
 16-bit tristate buffer            : 16
 8-bit tristate buffer             : 1
# Xors                             : 6
 1-bit xor2                        : 5
 16-bit xor2                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <dselect>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <daction>.
WARNING:Xst:1291 - FF/Latch <oPulseOnFallingEdge> is unconnected in block <denter>.
WARNING:Xst:2040 - Unit topbox: 32 multi-source signals are replaced by logic (pull-up yes): CPU/bus<0>, CPU/bus<10>, CPU/bus<11>, CPU/bus<12>, CPU/bus<13>, CPU/bus<14>, CPU/bus<15>, CPU/bus<1>, CPU/bus<2>, CPU/bus<3>, CPU/bus<4>, CPU/bus<5>, CPU/bus<6>, CPU/bus<7>, CPU/bus<8>, CPU/bus<9>, N11, N13, N15, N17, N19, N21, N23, N25, N27, N29, N3, N31, N33, N5, N7, N9.
WARNING:Xst:2042 - Unit alu: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.
WARNING:Xst:2042 - Unit rcvr: 8 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>.
WARNING:Xst:2042 - Unit register_1: 16 internal tristates are replaced by logic (pull-up yes): dout<0>, dout<10>, dout<11>, dout<12>, dout<13>, dout<14>, dout<15>, dout<1>, dout<2>, dout<3>, dout<4>, dout<5>, dout<6>, dout<7>, dout<8>, dout<9>.

Optimizing unit <topbox> ...

Optimizing unit <Debouncer> ...

Optimizing unit <controlclk> ...

Optimizing unit <idecode> ...

Optimizing unit <DisplayHex> ...

Optimizing unit <uart> ...

Optimizing unit <FrontPanel> ...

Optimizing unit <txmit> ...

Optimizing unit <rcvr> ...
Loading device for application Rf_Device from file '3s200.nph' in environment C:/Xilinx71.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <panel/denter/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/daction/oPulseOnFallingEdge> is unconnected in block <topbox>.
WARNING:Xst:1291 - FF/Latch <panel/dselect/oPulseOnFallingEdge> is unconnected in block <topbox>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block topbox, actual ratio is 30.
Forward register balancing over CPU/decoder/opdec78 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over CPU/decoder/opxor1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opand1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/decoder/opior1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_15, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/oplda1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opsrj1 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15.
Forward register balancing over Ker571 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/IR/dout_regvalue_EnableTr_INV56_SW0 of flipflops :
CPU/IR/regvalue_15, CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2101 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opinc41_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_13, CPU/IR/regvalue_0, CPU/IR/regvalue_14.
Forward register balancing over CPU/decoder/opdec41_SW2 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW0 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12, CPU/IR/regvalue_15.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV41_SW0_SW1 of flipflops :
CPU/IR/regvalue_14, CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over CPU/msend9 of flipflops :
CPU/ctl/sim/DEP/q, CPU/ctl/sim/EXAM/q.
Forward register balancing over CPU/ctl/sim/F1 of flipflops :
CPU/ctl/sim/EXAM/q, CPU/ctl/sim/DEP/q, CPU/ctl/sim/RUN/q.
Forward register balancing over CPU/decoder/opincdecx21_SW2 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_4, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/acc/dout_regvalue_EnableTr_INV29 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/oppush11_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppush11_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_12, CPU/IR/regvalue_11, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opframe31_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opincdecx21_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opldxa1_SW0_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opincdecx11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opinc41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opinc41_SW1 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_0.
Forward register balancing over CPU/decoder/opdec41_SW0 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec41_SW1 of flipflops :
CPU/IR/regvalue_0, CPU/IR/regvalue_5, CPU/IR/regvalue_1, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec51_SW2 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec51_SW3 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opstx21_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opframe31_SW1 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opstx21_SW1 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_1.
Forward register balancing over Ker2161_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/alu/_n00041_SW0 of flipflops :
CPU/IR/regvalue_1, CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n004722_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_1, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opspn11_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/decoder/opjmpa1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opframe1_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opincdecx21_SW1 of flipflops :
CPU/IR/regvalue_2, CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opincdecx21_SW3 of flipflops :
CPU/IR/regvalue_3, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_6.
Forward register balancing over CPU/decoder/opdec714_SW2 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/opdec51_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over CPU/decoder/opdec714_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_5, CPU/IR/regvalue_4, CPU/IR/regvalue_11.
Forward register balancing over CPU/decoder/oppush11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over CPU/decoder/opdec714_SW3 of flipflops :
CPU/IR/regvalue_6, CPU/IR/regvalue_4, CPU/IR/regvalue_12, CPU/IR/regvalue_11.
Forward register balancing over CPU/sendsum5_SW1 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/oppop11_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_4.
Forward register balancing over Ker161_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_6, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec74 of flipflops :
CPU/IR/regvalue_7, CPU/IR/regvalue_8, CPU/IR/regvalue_9, CPU/IR/regvalue_10.
Forward register balancing over CPU/senddiff3_SW0 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_12.
Forward register balancing over Ker2131_SW2_SW0 of flipflops :
CPU/IR/regvalue_12, CPU/IR/regvalue_13.
Forward register balancing over CPU/ctl/sim/Ker71 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/ctl/sim/_n00121 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/ctl/sim/_n00111 of flipflops :
CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2.
Forward register balancing over CPU/ctl/sim/_n00101 of flipflops :
CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1.
Forward register balancing over CPU/bus<0>__n0000<0>_N01_SW0 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_1, CPU/ctl/sim/counter_0.
Forward register balancing over CPU/decoder/opadd1 of flipflops :
CPU/IR/regvalue_13, CPU/IR/regvalue_14, CPU/IR/regvalue_15, CPU/IR/regvalue_12.
Forward register balancing over CPU/decoder/opdec41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW1_FRB, CPU/IR/regvalue_15, CPU/decoder/opdec41_SW2_FRB.
Forward register balancing over CPU/decoder/opinc41 of flipflops :
CPU/decoder/opdec74_FRB, CPU/decoder/opdec714_SW3_FRB, CPU/IR/regvalue_15, CPU/decoder/opinc41_SW2_FRB.
Forward register balancing over CPU/decoder/opldi11_SW0 of flipflops :
CPU/IR/regvalue_2, CPU/decoder/opdec51_SW3_FRB, CPU/IR/regvalue_0, CPU/IR/regvalue_5.
Forward register balancing over CPU/alu/_n00091_SW0 of flipflops :
CPU/IR/regvalue_5, CPU/IR/regvalue_1.
Forward register balancing over CPU/sendsum5_SW0 of flipflops :
CPU/decoder/opincdecx11_SW0_FRB, CPU/IR/regvalue_2, CPU/IR/regvalue_4, CPU/IR/regvalue_3.
Forward register balancing over Ker212_SW0 of flipflops :
CPU/IR/regvalue_4, CPU/IR/regvalue_3, CPU/decoder/opspn11_SW1_FRB, CPU/IR/regvalue_5.
Forward register balancing over CPU/decoder/opdec714 of flipflops :
CPU/decoder/opdec74_FRB, CPU/IR/regvalue_11, CPU/IR/regvalue_12, CPU/decoder/opdec78_FRB.
Forward register balancing over CPU/ctl/sim/_n00151 of flipflops :
CPU/ctl/sim/counter_2, CPU/ctl/sim/counter_0, CPU/ctl/sim/counter_1.
Register <CPU/decoder/oppop11_SW0_FRB> equivalent to <CPU/sendsum5_SW1_FRB> has been removed
Register <CPU/decoder/opinc41_SW1_FRB> equivalent to <CPU/decoder/opldxa1_SW0_SW0_FRB> has been removed
Register <CPU/alu/_n00091_SW0_FRB> equivalent to <Ker2161_SW0_FRB> has been removed
Register <CPU/decoder/opdec51_SW3_FRB> equivalent to <CPU/decoder/opdec51_SW2_FRB> has been removed
Register <CPU/decoder/opdec41_SW1_FRB> equivalent to <CPU/decoder/opdec41_SW0_FRB> has been removed
FlipFlop CPU/IR/regvalue_1 has been replicated 1 time(s)
FlipFlop CPU/IR/regvalue_2 has been replicated 2 time(s)
FlipFlop CPU/ctl/sim/_n00111_FRB has been replicated 7 time(s)
FlipFlop CPU/decoder/opdec714_FRB has been replicated 1 time(s)
FlipFlop loadnow has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     617  out of   1920    32%  
 Number of Slice Flip Flops:           436  out of   3840    11%  
 Number of 4 input LUTs:              1082  out of   3840    28%  
 Number of bonded IOBs:                 74  out of    173    42%  
 Number of GCLKs:                        2  out of      8    25%  
 Number of DCM_ADVs:                     1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+--------------------------------+-------+
Clock Signal                       | Clock buffer(FF name)          | Load  |
-----------------------------------+--------------------------------+-------+
clkin                              | CPU/ctl/clockgen/DCM_INST:CLKFX| 436   |
-----------------------------------+--------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 13.584ns (Maximum Frequency: 73.618MHz)
   Minimum input arrival time before clock: 10.967ns
   Maximum output required time after clock: 23.172ns
   Maximum combinational path delay: 15.112ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd c:\blue71/_ngo -uc tobox.ucf -p
xc3s200-ft256-4 topbox.ngc topbox.ngd 

Reading NGO file 'C:/blue71/topbox.ngc' ...

Applying constraints in "tobox.ucf" to the design...

Checking timing specifications ...
   CLKFX: TS_CPU_ctl_clockgen_CLKFX_BUF=PERIOD CPU_ctl_clockgen_CLKFX_BUF
TS_clkin*0.700000 HIGH 50.000000%
   CLKFX180: TS_CPU_ctl_wclk=PERIOD CPU_ctl_wclk TS_clkin*0.700000 PHASE +
20.408000 nS HIGH 50.000000%
WARNING:XdmHelpers:662 - Period specification "TS_CPU_ctl_wclk" references the
   TNM group "CPU_ctl_wclk", which contains both pads and synchronous elements.
   The timing analyzer will ignore the pads for this specification. You might
   want to use a qualifier (e.g. "FFS") on the TNM property to remove the pads
   from this group.
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Writing NGD file "topbox.ngd" ...

Writing NGDBUILD log file "topbox.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s200ft256-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running timing-driven packing...

Phase 1.1
Phase 1.1 (Checksum:98d1ef) REAL time: 0 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.4
..............
Phase 4.4 (Checksum:26259fc) REAL time: 3 secs 

Phase 5.28
Phase 5.28 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.8
.....................
........
........................................
...............
...............
Phase 6.8 (Checksum:ab675f) REAL time: 11 secs 

Phase 7.29
Phase 7.29 (Checksum:42c1d79) REAL time: 11 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 11 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 21 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 21 secs 


Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:         410 out of   3,840   10%
  Number of 4 input LUTs:           1,131 out of   3,840   29%
Logic Distribution:
  Number of occupied Slices:                          679 out of   1,920   35%
    Number of Slices containing only related logic:     679 out of     679  100%
    Number of Slices containing unrelated logic:          0 out of     679    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,136 out of   3,840   29%
  Number used as logic:              1,131
  Number used as a route-thru:           5
  Number of bonded IOBs:               74 out of     173   42%
    IOB Flip Flops:                    26
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  18,144
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  133 MB

Mapping completed.
See MAP report file "topbox_map.mrp" for details.




Started process "Place & Route".




Constraints file: topbox.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Device speed data version:  "PRODUCTION 1.35 2005-01-22".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to
   achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of DCMs                      1 out of 4      25%
   Number of External IOBs            74 out of 173    42%
      Number of LOCed IOBs            74 out of 74    100%

   Number of Slices                  679 out of 1920   35%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   High (set by user)
Router effort level (-rl):    High (set by user)

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 5 secs 

Starting Router

Phase 1: 4917 unrouted;       REAL time: 5 secs 

Phase 2: 4563 unrouted;       REAL time: 5 secs 

Phase 3: 2325 unrouted;       REAL time: 6 secs 

Phase 4: 2325 unrouted; (0)      REAL time: 6 secs 

Phase 5: 2325 unrouted; (0)      REAL time: 7 secs 

Phase 6: 2325 unrouted; (0)      REAL time: 7 secs 

Phase 7: 0 unrouted; (0)      REAL time: 15 secs 

Phase 8: 0 unrouted; (0)      REAL time: 16 secs 


Total REAL time to Router completion: 17 secs 
Total CPU time to Router completion: 16 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 clk |      BUFGMUX2| No   |  336 |  0.041     |  1.051      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_clkin = PERIOD TIMEGRP "clkin" 35 MHz  | N/A        | N/A        | N/A  
  HIGH 50%                                  |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_clockgen_CLKFX_BUF = PERIOD TI | 40.816ns   | 27.694ns   | 5    
  MEGRP "CPU_ctl_clockgen_CLKFX_BUF"        |            |            |      
    TS_clkin * 0.7 HIGH 50%                 |            |            |      
--------------------------------------------------------------------------------
  TS_CPU_ctl_wclk = PERIOD TIMEGRP "CPU_ctl | 40.816ns   | 40.530ns   | 10   
  _wclk" TS_clkin * 0.7 PHASE 20.408 ns     |            |            |      
       HIGH 50%                             |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 19 secs 
Total CPU time to PAR completion: 18 secs 

Peak Memory Usage:  95 MB

Placer: Not run.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 1

Writing design to file topbox.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s200.nph' in environment
C:/Xilinx71.
   "topbox" is an NCD, version 3.1, device xc3s200, package ft256, speed -4
WARNING:Timing:2798 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/wclk from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).
WARNING:Timing:2798 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the minimum period (maximum frequency) of 41666
   ps (24.00 Mhz).
WARNING:Timing:2799 - The output clock CPU/ctl/clockgen/CLKFX_BUF from DCM
   CPU/ctl/clockgen/DCM_INST has a period (frequency) specification of 40815 ps
   (24.50 Mhz).  This violates the maximum period (minimum frequency) of 4761 ps
   (210.04 Mhz).

Analysis completed Sat Sep 30 20:50:01 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 4
Total time: 3 secs 







Started process "Generate Programming File".

INFO:PhysDesignRules:772 - To achieve optimal frequency synthesis performance
   with the CLKFX and CLKFX180 outputs of the DCM comp
   CPU/ctl/clockgen/DCM_INST/CPU/ctl/clockgen/DCM_INST, consult the device
   Interactive Data Sheet.