Subversion Repositories bustap-jtag

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#
# Xilinx Core Generator version 14.2
# Date: Tue Nov 20 02:34:08 2012
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
#
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#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7z020
SET devicefamily = zynq
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = clg400
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
# END Select
# BEGIN Parameters
CSET asynchronous_input_port_width=8
CSET asynchronous_output_port_width=8
CSET component_name=chipscope_vio_fifo
CSET constraint_type=external
CSET enable_asynchronous_input_port=false
CSET enable_asynchronous_output_port=false
CSET enable_synchronous_input_port=true
CSET enable_synchronous_output_port=true
CSET example_design=true
CSET invert_clock_input=false
CSET synchronous_input_port_width=92
CSET synchronous_output_port_width=2
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-21T03:12:17Z
# END Extra information
GENERATE
# CRC: 9f8da0d5