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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML> <HEAD> <META HTTP-EQUIV="CONTENT-TYPE" CONTENT="text/html; charset=utf-8"> <TITLE>start</TITLE> <META NAME="GENERATOR" CONTENT="LibreOffice 3.6 (Linux)"> <META NAME="CREATED" CONTENT="0;0"> <META NAME="CHANGEDBY" CONTENT="Ouabache Designworks"> <META NAME="CHANGED" CONTENT="20130817;8220700"> <META NAME="KEYWORDS" CONTENT="start"> <META NAME="Info 3" CONTENT=""> <META NAME="Info 4" CONTENT=""> <META NAME="date" CONTENT="2008-01-08T12:01:41-0500"> <META NAME="robots" CONTENT="index,follow"> <META NAME="CHANGEDBY" CONTENT="Ouabache Designworks"> </HEAD> <BODY LANG="en-US" DIR="LTR"> <DIV ID="toc__header" DIR="LTR"> <H1><A NAME="socgen ip"></A>CDE LIBRARY: </H1> <P>The Common Design Environment (CDE) is a library of verilog IP modules for use in fpga and asic designs. One problem that we face is that not all rtl code is synthesisable into all target processes. The CDE project seeks to identify this problem code and provide documented and functioning models for each case. A CDE module will isolate the problem code inside a single module that can be easily replaced when the design is targeted to a process that requires substitution of custom hard macros. This can be done without touching the users rtl code so that a single code base can support both fpga and asic targets without modification.</P> <P><BR><BR> </P> <P>CDE is part of the SOCEN design environment and uses IP-Xact module descriptors. Documention is autogenerated and uses the gEDA tool set. </P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> <P><BR><BR> </P> </DIV> <DIV ID="toc__inside" DIR="LTR"> <UL> <LI><P STYLE="margin-bottom: 0in"><A HREF="#IPModules">IP Modules</A></P> <UL> <LI><P><A HREF="../ip/pad/doc/html/component.html">IO Pads</A></P> <LI><P><A HREF="../ip/sram/doc/html/component.html">Synchronous Rams</A></P> </UL> </UL> </DIV> <P><BR><BR> </P> </BODY> </HTML>