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URL https://opencores.org/ocsvn/cde/cde/trunk

Subversion Repositories cde

[/] [cde/] [trunk/] [ip/] [sram/] [doc/] [sch/] [sram_timing.sch] - Rev 2

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v 20121203 2
B 2800 600 4300 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 3000 2700 9 10 1 0 0 0 1
addr
T 3100 3000 9 10 1 0 0 0 1
clk
T 3200 2400 9 10 1 0 0 0 1
cs
T 3200 2100 9 10 1 0 0 0 1
wr
T 3200 1800 9 10 1 0 0 0 1
rd
T 3200 1500 9 10 1 0 0 0 1
be
T 3000 1200 9 10 1 0 0 0 1
wdata
T 3100 900 9 10 1 0 0 0 1
rdata
L 3600 3000 3700 3000 3 0 1 0 -1 -1
L 3700 3000 3800 3200 3 0 1 0 -1 -1
L 3800 3200 4100 3200 3 0 1 0 -1 -1
L 4100 3200 4200 3000 3 0 1 0 -1 -1
L 4200 3000 4500 3000 3 0 1 0 -1 -1
L 4500 3000 4600 3200 3 0 1 0 -1 -1
L 4600 3200 4900 3200 3 0 1 0 -1 -1
L 4900 3200 5000 3000 3 0 1 0 -1 -1
L 5000 3000 5300 3000 3 0 1 0 -1 -1
L 5300 3000 5400 3200 3 0 1 0 -1 -1
L 5400 3200 5700 3200 3 0 1 0 -1 -1
L 5700 3200 5800 3000 3 0 1 0 -1 -1
L 5800 3000 6100 3000 3 0 1 0 -1 -1
L 6100 3000 6200 3200 3 0 1 0 -1 -1
L 6200 3200 6500 3200 3 0 1 0 -1 -1
L 3600 2700 4500 2700 3 0 1 0 -1 -1
L 4500 2700 4600 2900 3 0 1 0 -1 -1
L 4600 2900 5300 2900 3 0 1 0 -1 -1
L 5300 2900 5400 2700 3 0 1 0 -1 -1
L 5400 2700 6500 2700 3 0 1 0 -1 -1
L 3600 2900 4500 2900 3 0 1 0 -1 -1
L 4500 2900 4600 2700 3 0 1 0 -1 -1
L 4600 2700 5300 2700 3 0 1 0 -1 -1
L 5300 2700 5400 2900 3 0 1 0 -1 -1
L 5400 2900 6500 2900 3 0 1 0 -1 -1
L 3600 2400 4500 2400 3 0 1 0 -1 -1
L 4500 2400 4600 2600 3 0 1 0 -1 -1
L 4600 2600 5300 2600 3 0 1 0 -1 -1
L 5300 2600 5400 2400 3 0 1 0 -1 -1
L 5400 2400 6500 2400 3 0 1 0 -1 -1
L 3600 2100 4500 2100 3 0 1 0 -1 -1
L 4500 2100 4600 2300 3 0 1 0 -1 -1
L 4600 2300 5300 2300 3 0 1 0 -1 -1
L 5300 2300 5400 2100 3 0 1 0 -1 -1
L 5400 2100 6500 2100 3 0 1 0 -1 -1
L 3600 1800 4500 1800 3 0 1 0 -1 -1
L 4500 1800 4600 2000 3 0 1 0 -1 -1
L 4600 2000 5300 2000 3 0 1 0 -1 -1
L 5300 2000 5400 1800 3 0 1 0 -1 -1
L 5400 1800 6500 1800 3 0 1 0 -1 -1
L 3600 1500 4500 1500 3 0 1 0 -1 -1
L 4500 1500 4600 1700 3 0 1 0 -1 -1
L 4600 1700 5300 1700 3 0 1 0 -1 -1
L 5300 1700 5400 1500 3 0 1 0 -1 -1
L 5400 1500 6500 1500 3 0 1 0 -1 -1
L 3600 1200 4500 1200 3 0 1 0 -1 -1
L 4500 1200 4600 1400 3 0 1 0 -1 -1
L 4600 1400 5300 1400 3 0 1 0 -1 -1
L 5300 1400 5400 1200 3 0 1 0 -1 -1
L 5400 1200 6500 1200 3 0 1 0 -1 -1
L 3600 1400 4500 1400 3 0 1 0 -1 -1
L 4500 1400 4600 1200 3 0 1 0 -1 -1
L 4600 1200 5300 1200 3 0 1 0 -1 -1
L 5300 1200 5400 1400 3 0 1 0 -1 -1
L 5400 1400 6500 1400 3 0 1 0 -1 -1
L 3600 900 5300 900 3 0 1 0 -1 -1
L 5300 900 5400 1100 3 0 1 0 -1 -1
L 5400 1100 6100 1100 3 0 1 0 -1 -1
L 6100 1100 6200 900 3 0 1 0 -1 -1
L 6200 900 6500 900 3 0 1 0 -1 -1
L 3600 1100 5300 1100 3 0 1 0 -1 -1
L 5300 1100 5400 900 3 0 1 0 -1 -1
L 5400 900 6100 900 3 0 1 0 -1 -1
L 6100 900 6200 1100 3 0 1 0 -1 -1
L 6200 1100 6500 1100 3 0 1 0 -1 -1
T 4720 2740 9 10 1 0 0 0 1
valid
T 4730 1250 9 10 1 0 0 0 1
valid
T 5540 950 9 10 1 0 0 0 1
valid
T 4100 940 9 10 1 0 0 0 1
default
T 6310 950 9 10 1 0 0 0 1
default

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