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##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Feb 20 10:24:39 2013
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_v_7.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_dram_7
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=rom
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: fc5a2759