Subversion Repositories fat_32_file_parser

Welcome to Xilinx CORE Generator.
Help system initialized.
The IP Catalog has been reloaded.
Opening project file
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/coregen.cgp.
Recustomize and Generate (Under Current Project Settings)INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
ERROR:sim - Unable to find /home/craig/Documents/craigs/projectV/nexys2/ps2
ERROR:sim -    keyboard/ps2keyboard/lat0-12.coe
ERROR:sim -    Coregen is looking for
   /home/craig/Documents/craigs/projectV/nexys2/ps2
ERROR:sim -    keyboard/ps2keyboard/lat0-12.coe
ERROR:sim - Unable to find /home/craig/Documents/craigs/projectV/nexys2/ps2
ERROR:sim -    keyboard/ps2keyboard/lat0-12.coe
ERROR:sim -    Coregen is looking for
   /home/craig/Documents/craigs/projectV/nexys2/ps2
ERROR:sim -    keyboard/ps2keyboard/lat0-12.coe
ERROR:sim - An invalid core configuration has been detected during
ERROR:sim -    Customization. Core parameters will be reset to their default
   values.
Resolving generics for 'FONT_MEM'...
Applying external generics to 'FONT_MEM'...
Delivering associated files for 'FONT_MEM'...
WARNING:sim - Component blk_mem_gen_v7_2 does not have a valid model name for
   VHDL synthesis
Delivering EJava files for 'FONT_MEM'...
Generating implementation netlist for 'FONT_MEM'...
INFO:sim - Pre-processing HDL files for 'FONT_MEM'...
Running synthesis for 'FONT_MEM'
Running ngcbuild...
Writing VHO instantiation template for 'FONT_MEM'...
Writing VHDL instantiation wrapper for 'FONT_MEM'...
Writing VHDL behavioral simulation model for 'FONT_MEM'...
WARNING:sim - No files were found for the view xilinx_documentation
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating metadata file...
Generating ISE project file for 'FONT_MEM'...
Generating ISE project...
XCO file found: FONT_MEM.xco
XMDF file found: FONT_MEM_xmdf.tcl
Adding
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.asy
-view all -origin_type imported
Adding
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc
-view all -origin_type created
Checking file
"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc"
for project device match ...
File
"/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.ngc"
device information matches project device.
Adding
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
-view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
   " into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vho
-view all -origin_type imported
Adding
/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_synth.v
hd -view all -origin_type created
INFO:HDLCompiler:1061 - Parsing VHDL file
   "/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_syn
   th.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Duplicate Design Unit 'FONT_MEM' found in library 'work'
WARNING:ProjectMgmt -   
   "/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM.vhd
   " line 43 (active)
WARNING:ProjectMgmt -   
   "/home/craig/Documents/CW/Git_Repos/hw_client/ipcore_dir/tmp/_cg/FONT_MEM_syn
   th.vhd" line 64 
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/FONT_MEM"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
Closed project file.