Subversion Repositories funbase_ip_library

<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
 <component
   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 <parameter name="bonusData"><![CDATA[bonusData 
{
   element $${FILENAME}
   {
   }
   element jtag_uart_1.avalon_jtag_slave
   {
      datum baseAddress
      {
         value = "12872";
         type = "String";
      }
   }
   element hibi_pe_dma_0.avalon_slave_0
   {
      datum _lockedAddress
      {
         value = "0";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "12288";
         type = "String";
      }
   }
   element clk_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element sysid_qsys_1.control_slave
   {
      datum baseAddress
      {
         value = "12864";
         type = "String";
      }
   }
   element hibi_pe_dma_0
   {
      datum _sortIndex
      {
         value = "8";
         type = "int";
      }
   }
   element nios2_qsys_1.jtag_debug_module
   {
      datum baseAddress
      {
         value = "10240";
         type = "String";
      }
   }
   element jtag_uart_1
   {
      datum _sortIndex
      {
         value = "7";
         type = "int";
      }
   }
   element nios2_qsys_1
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element onchip_memory2_1
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element sdram_0.s1
   {
      datum baseAddress
      {
         value = "33554432";
         type = "String";
      }
   }
   element onchip_memory2_1.s1
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "0";
         type = "String";
      }
   }
   element timer_0.s1
   {
      datum baseAddress
      {
         value = "12800";
         type = "String";
      }
   }
   element timer_1.s1
   {
      datum baseAddress
      {
         value = "12832";
         type = "String";
      }
   }
   element onchip_memory2_1.s2
   {
      datum _lockedAddress
      {
         value = "1";
         type = "boolean";
      }
      datum baseAddress
      {
         value = "0";
         type = "String";
      }
   }
   element sdram_0
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
      datum megawizard_uipreferences
      {
         value = "{output_language=VERILOG, output_directory=D:\\user\\matilail\\repos\\opencores_lib\\Altera\\ip.hwp.cpu\\nios_ii_sdram\\1.2\\hdl}";
         type = "String";
      }
   }
   element sysid_qsys_1
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element timer_0
   {
      datum _sortIndex
      {
         value = "5";
         type = "int";
      }
   }
   element timer_1
   {
      datum _sortIndex
      {
         value = "6";
         type = "int";
      }
   }
}
]]></parameter>
 <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
 <parameter name="device" value="EP2C35F672C6" />
 <parameter name="deviceFamily" value="Cyclone II" />
 <parameter name="deviceSpeedGrade" value="6" />
 <parameter name="fabricMode" value="QSYS" />
 <parameter name="generateLegacySim" value="false" />
 <parameter name="generationId" value="0" />
 <parameter name="globalResetBus" value="false" />
 <parameter name="hdlLanguage" value="VERILOG" />
 <parameter name="maxAdditionalLatency" value="1" />
 <parameter name="projectName" value="" />
 <parameter name="sopcBorderPoints" value="false" />
 <parameter name="systemHash" value="1" />
 <parameter name="timeStamp" value="1370947901242" />
 <parameter name="useTestBenchNamingPattern" value="false" />
 <instanceScript></instanceScript>
 <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
 <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" />
 <interface name="sdram_0" internal="sdram_0.wire" type="conduit" dir="end" />
 <interface
   name="hibi_pe_dma"
   internal="hibi_pe_dma_0.conduit_end"
   type="conduit"
   dir="end" />
 <module kind="clock_source" version="12.1" enabled="1" name="clk_0">
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="clockFrequencyKnown" value="true" />
  <parameter name="inputClockFrequency" value="0" />
  <parameter name="resetSynchronousEdges" value="NONE" />
 </module>
 <module
   kind="altera_nios2_qsys"
   version="12.1"
   enabled="1"
   name="nios2_qsys_1">
  <parameter name="setting_showUnpublishedSettings" value="false" />
  <parameter name="setting_showInternalSettings" value="false" />
  <parameter name="setting_preciseSlaveAccessErrorException" value="false" />
  <parameter name="setting_preciseIllegalMemAccessException" value="false" />
  <parameter name="setting_preciseDivisionErrorException" value="false" />
  <parameter name="setting_performanceCounter" value="false" />
  <parameter name="setting_illegalMemAccessDetection" value="false" />
  <parameter name="setting_illegalInstructionsTrap" value="false" />
  <parameter name="setting_fullWaveformSignals" value="false" />
  <parameter name="setting_extraExceptionInfo" value="false" />
  <parameter name="setting_exportPCB" value="false" />
  <parameter name="setting_debugSimGen" value="false" />
  <parameter name="setting_clearXBitsLDNonBypass" value="true" />
  <parameter name="setting_bit31BypassDCache" value="true" />
  <parameter name="setting_bigEndian" value="false" />
  <parameter name="setting_export_large_RAMs" value="false" />
  <parameter name="setting_asic_enabled" value="false" />
  <parameter name="setting_asic_synopsys_translate_on_off" value="false" />
  <parameter name="setting_oci_export_jtag_signals" value="false" />
  <parameter name="setting_bhtIndexPcOnly" value="false" />
  <parameter name="setting_avalonDebugPortPresent" value="false" />
  <parameter name="setting_alwaysEncrypt" value="true" />
  <parameter name="setting_allowFullAddressRange" value="false" />
  <parameter name="setting_activateTrace" value="true" />
  <parameter name="setting_activateTestEndChecker" value="false" />
  <parameter name="setting_activateMonitors" value="true" />
  <parameter name="setting_activateModelChecker" value="false" />
  <parameter name="setting_HDLSimCachesCleared" value="true" />
  <parameter name="setting_HBreakTest" value="false" />
  <parameter name="muldiv_divider" value="false" />
  <parameter name="mpu_useLimit" value="false" />
  <parameter name="mpu_enabled" value="false" />
  <parameter name="mmu_enabled" value="false" />
  <parameter name="mmu_autoAssignTlbPtrSz" value="true" />
  <parameter name="manuallyAssignCpuID" value="true" />
  <parameter name="debug_triggerArming" value="true" />
  <parameter name="debug_embeddedPLL" value="true" />
  <parameter name="debug_debugReqSignals" value="false" />
  <parameter name="debug_assignJtagInstanceID" value="false" />
  <parameter name="dcache_omitDataMaster" value="false" />
  <parameter name="cpuReset" value="false" />
  <parameter name="is_hardcopy_compatible" value="false" />
  <parameter name="setting_shadowRegisterSets" value="0" />
  <parameter name="mpu_numOfInstRegion" value="8" />
  <parameter name="mpu_numOfDataRegion" value="8" />
  <parameter name="mmu_TLBMissExcOffset" value="0" />
  <parameter name="debug_jtagInstanceID" value="0" />
  <parameter name="resetOffset" value="0" />
  <parameter name="exceptionOffset" value="32" />
  <parameter name="cpuID" value="16777216" />
  <parameter name="cpuID_stored" value="16777216" />
  <parameter name="breakOffset" value="32" />
  <parameter name="userDefinedSettings" value="" />
  <parameter name="resetSlave" value="sdram_0.s1" />
  <parameter name="mmu_TLBMissExcSlave" value="" />
  <parameter name="exceptionSlave" value="sdram_0.s1" />
  <parameter name="breakSlave">nios2_qsys_1.jtag_debug_module</parameter>
  <parameter name="setting_perfCounterWidth" value="32" />
  <parameter name="setting_interruptControllerType" value="Internal" />
  <parameter name="setting_branchPredictionType" value="Automatic" />
  <parameter name="setting_bhtPtrSz" value="8" />
  <parameter name="muldiv_multiplierType" value="EmbeddedMulFast" />
  <parameter name="mpu_minInstRegionSize" value="12" />
  <parameter name="mpu_minDataRegionSize" value="12" />
  <parameter name="mmu_uitlbNumEntries" value="4" />
  <parameter name="mmu_udtlbNumEntries" value="6" />
  <parameter name="mmu_tlbPtrSz" value="7" />
  <parameter name="mmu_tlbNumWays" value="16" />
  <parameter name="mmu_processIDNumBits" value="8" />
  <parameter name="impl" value="Fast" />
  <parameter name="icache_size" value="4096" />
  <parameter name="icache_ramBlockType" value="Automatic" />
  <parameter name="icache_numTCIM" value="0" />
  <parameter name="icache_burstType" value="None" />
  <parameter name="dcache_bursts" value="false" />
  <parameter name="debug_level" value="Level1" />
  <parameter name="debug_OCIOnchipTrace" value="_128" />
  <parameter name="dcache_size" value="2048" />
  <parameter name="dcache_ramBlockType" value="Automatic" />
  <parameter name="dcache_numTCDM" value="0" />
  <parameter name="dcache_lineSize" value="32" />
  <parameter name="instAddrWidth" value="26" />
  <parameter name="dataAddrWidth" value="26" />
  <parameter name="tightlyCoupledDataMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledDataMaster3AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster0AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster1AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster2AddrWidth" value="1" />
  <parameter name="tightlyCoupledInstructionMaster3AddrWidth" value="1" />
  <parameter name="instSlaveMapParam"><![CDATA[<address-map><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></parameter>
  <parameter name="dataSlaveMapParam"><![CDATA[<address-map><slave name='onchip_memory2_1.s1' start='0x0' end='0x2000' /><slave name='nios2_qsys_1.jtag_debug_module' start='0x2800' end='0x3000' /><slave name='hibi_pe_dma_0.avalon_slave_0' start='0x3000' end='0x3200' /><slave name='timer_0.s1' start='0x3200' end='0x3220' /><slave name='timer_1.s1' start='0x3220' end='0x3240' /><slave name='sysid_qsys_1.control_slave' start='0x3240' end='0x3248' /><slave name='jtag_uart_1.avalon_jtag_slave' start='0x3248' end='0x3250' /><slave name='sdram_0.s1' start='0x2000000' end='0x2800000' /></address-map>]]></parameter>
  <parameter name="clockFrequency" value="50000000" />
  <parameter name="deviceFamilyName" value="Cyclone II" />
  <parameter name="internalIrqMaskSystemInfo" value="15" />
  <parameter name="customInstSlavesSystemInfo" value="&lt;info/&gt;" />
  <parameter name="deviceFeaturesSystemInfo">NOT_LISTED 0 INSTALLED 1 IS_DEFAULT_FAMILY 0 ADDRESS_STALL 1 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FITTER_USE_FALLING_EDGE_DELAY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 0 HAS_ADVANCED_IO_TIMING_SUPPORT 0 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 0 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 1 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 1 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_EARLY_TIMING_ESTIMATE_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 0 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_SMART_RECOMPILE_SUPPORT 1 HAS_JITTER_SUPPORT 0 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 0 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 0 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 1 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 0 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 0 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 1 HAS_SPLIT_IO_SUPPORT 0 HAS_SPLIT_LC_SUPPORT 1 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 0 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 1 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 0 IS_CONFIG_ROM 0 IS_HARDCOPY_FAMILY 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 1 M512_MEMORY 0 M9K_MEMORY 0 MLAB_MEMORY 0 MRAM_MEMORY 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 1 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_SUPPORT 1 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 0 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 0 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RISEFALL_SUPPORT_IS_HIDDEN 1 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 1 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 0 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 1 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 0 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 0 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_THIRD_GENERATION_TIMING_MODELS_TIS 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 0 USE_ADVANCED_IO_TIMING_BY_DEFAULT 0 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 0 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 0 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 0 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 0</parameter>
  <parameter name="tightlyCoupledDataMaster0MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster1MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster2MapParam" value="" />
  <parameter name="tightlyCoupledDataMaster3MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster0MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster1MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster2MapParam" value="" />
  <parameter name="tightlyCoupledInstructionMaster3MapParam" value="" />
 </module>
 <module
   kind="altera_avalon_onchip_memory2"
   version="12.1"
   enabled="1"
   name="onchip_memory2_1">
  <parameter name="allowInSystemMemoryContentEditor" value="false" />
  <parameter name="autoInitializationFileName">$${FILENAME}_onchip_memory2_1</parameter>
  <parameter name="blockType" value="AUTO" />
  <parameter name="dataWidth" value="32" />
  <parameter name="deviceFamily" value="Cyclone II" />
  <parameter name="dualPort" value="true" />
  <parameter name="initMemContent" value="true" />
  <parameter name="initializationFileName" value="onchip_memory2_1" />
  <parameter name="instanceID" value="NONE" />
  <parameter name="memorySize" value="8192" />
  <parameter name="readDuringWriteMode" value="DONT_CARE" />
  <parameter name="simAllowMRAMContentsFile" value="false" />
  <parameter name="simMemInitOnlyFilename" value="0" />
  <parameter name="singleClockOperation" value="false" />
  <parameter name="slave1Latency" value="1" />
  <parameter name="slave2Latency" value="1" />
  <parameter name="useNonDefaultInitFile" value="false" />
  <parameter name="useShallowMemBlocks" value="false" />
  <parameter name="writable" value="true" />
 </module>
 <module
   kind="altera_avalon_jtag_uart"
   version="12.1"
   enabled="1"
   name="jtag_uart_1">
  <parameter name="allowMultipleConnections" value="false" />
  <parameter name="avalonSpec" value="2.0" />
  <parameter name="hubInstanceID" value="0" />
  <parameter name="readBufferDepth" value="64" />
  <parameter name="readIRQThreshold" value="8" />
  <parameter name="simInputCharacterStream" value="" />
  <parameter name="simInteractiveOptions">INTERACTIVE_ASCII_OUTPUT</parameter>
  <parameter name="useRegistersForReadBuffer" value="false" />
  <parameter name="useRegistersForWriteBuffer" value="false" />
  <parameter name="useRelativePathForSimFile" value="false" />
  <parameter name="writeBufferDepth" value="64" />
  <parameter name="writeIRQThreshold" value="8" />
 </module>
 <module
   kind="altera_avalon_sysid_qsys"
   version="12.1"
   enabled="1"
   name="sysid_qsys_1">
  <parameter name="id" value="16777216" />
  <parameter name="timestamp" value="0" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="50000000" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone II" />
 </module>
 <module kind="altera_avalon_timer" version="12.1" enabled="1" name="timer_0">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="50000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <module kind="altera_avalon_timer" version="12.1" enabled="1" name="timer_1">
  <parameter name="alwaysRun" value="false" />
  <parameter name="counterSize" value="32" />
  <parameter name="fixedPeriod" value="false" />
  <parameter name="period" value="1" />
  <parameter name="periodUnits" value="MSEC" />
  <parameter name="resetOutput" value="false" />
  <parameter name="snapshot" value="true" />
  <parameter name="systemFrequency" value="50000000" />
  <parameter name="timeoutPulseOutput" value="false" />
  <parameter name="timerPreset" value="CUSTOM" />
 </module>
 <module
   kind="altera_avalon_new_sdram_controller"
   version="12.1"
   enabled="1"
   name="sdram_0">
  <parameter name="TAC" value="5.5" />
  <parameter name="TMRD" value="3" />
  <parameter name="TRCD" value="20.0" />
  <parameter name="TRFC" value="70.0" />
  <parameter name="TRP" value="20.0" />
  <parameter name="TWR" value="14.0" />
  <parameter name="casLatency" value="3" />
  <parameter name="clockRate" value="50000000" />
  <parameter name="columnWidth" value="8" />
  <parameter name="dataWidth" value="16" />
  <parameter name="generateSimulationModel" value="false" />
  <parameter name="initNOPDelay" value="0.0" />
  <parameter name="initRefreshCommands" value="2" />
  <parameter name="masteredTristateBridgeSlave" value="" />
  <parameter name="model" value="custom" />
  <parameter name="numberOfBanks" value="4" />
  <parameter name="numberOfChipSelects" value="1" />
  <parameter name="pinsSharedViaTriState" value="false" />
  <parameter name="powerUpDelay" value="100.0" />
  <parameter name="refreshPeriod" value="15.625" />
  <parameter name="registerDataIn" value="true" />
  <parameter name="rowWidth" value="12" />
 </module>
 <module kind="hibi_pe_dma" version="1.0" enabled="1" name="hibi_pe_dma_0">
  <parameter name="data_width_g" value="32" />
  <parameter name="addr_width_g" value="32" />
  <parameter name="words_width_g" value="16" />
  <parameter name="n_stream_chans_g" value="2" />
  <parameter name="n_packet_chans_g" value="2" />
  <parameter name="n_chans_bits_g" value="3" />
  <parameter name="hibi_addr_cmp_lo_g" value="0" />
  <parameter name="hibi_addr_cmp_hi_g" value="31" />
  <parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
 </module>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.instruction_master"
   end="nios2_qsys_1.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x2800" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="nios2_qsys_1.jtag_debug_module">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x2800" />
 </connection>
 <connection kind="clock" version="12.1" start="clk_0.clk" end="sdram_0.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="sdram_0.reset" />
 <connection kind="clock" version="12.1" start="clk_0.clk" end="timer_1.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="timer_1.reset" />
 <connection kind="clock" version="12.1" start="clk_0.clk" end="timer_0.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="timer_0.reset" />
 <connection kind="clock" version="12.1" start="clk_0.clk" end="sysid_qsys_1.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="sysid_qsys_1.reset" />
 <connection kind="clock" version="12.1" start="clk_0.clk" end="jtag_uart_1.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="jtag_uart_1.reset" />
 <connection
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="onchip_memory2_1.clk2" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="onchip_memory2_1.reset2" />
 <connection
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="onchip_memory2_1.clk1" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="onchip_memory2_1.reset1" />
 <connection kind="clock" version="12.1" start="clk_0.clk" end="nios2_qsys_1.clk" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="nios2_qsys_1.reset_n" />
 <connection
   kind="interrupt"
   version="12.1"
   start="nios2_qsys_1.d_irq"
   end="jtag_uart_1.irq">
  <parameter name="irqNumber" value="0" />
 </connection>
 <connection
   kind="interrupt"
   version="12.1"
   start="nios2_qsys_1.d_irq"
   end="timer_1.irq">
  <parameter name="irqNumber" value="1" />
 </connection>
 <connection
   kind="interrupt"
   version="12.1"
   start="nios2_qsys_1.d_irq"
   end="timer_0.irq">
  <parameter name="irqNumber" value="2" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="jtag_uart_1.avalon_jtag_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x3248" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="timer_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x3220" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="timer_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x3200" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="sysid_qsys_1.control_slave">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x3240" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="sdram_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02000000" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.instruction_master"
   end="sdram_0.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x02000000" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="onchip_memory2_1.s1">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="hibi_pe_dma_0.clock" />
 <connection
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="hibi_pe_dma_0.clock_sink_reset" />
 <connection
   kind="avalon"
   version="12.1"
   start="nios2_qsys_1.data_master"
   end="hibi_pe_dma_0.avalon_slave_0">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x3000" />
 </connection>
 <connection
   kind="interrupt"
   version="12.1"
   start="nios2_qsys_1.d_irq"
   end="hibi_pe_dma_0.interrupt_sender">
  <parameter name="irqNumber" value="3" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="hibi_pe_dma_0.avalon_master"
   end="onchip_memory2_1.s2">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
 <connection
   kind="avalon"
   version="12.1"
   start="hibi_pe_dma_0.avalon_master_1"
   end="onchip_memory2_1.s2">
  <parameter name="arbitrationPriority" value="1" />
  <parameter name="baseAddress" value="0x0000" />
 </connection>
</system>