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<center><font size=+3><b>OPENCORES.ORG</b></font>
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<font SIZE="2">-- VHDL structural description generated from `ram`
<p>-- date : Tue Feb 20 23:00:09 2001</p>
<p> </p>
<p>-- Entity Declaration</p>
<p>ENTITY ram IS</p>
<p>PORT (</p>
<p>rws : in BIT; -- rws</p>
<p>cs : in BIT; -- cs</p>
<p>res : in BIT; -- res</p>
<p>c : in BIT_VECTOR (0 TO 15); -- c</p>
<p>io0 : inout BIT; -- io0</p>
<p>io1 : inout BIT; -- io1</p>
<p>io2 : inout BIT; -- io2</p>
<p>io3 : inout BIT; -- io3</p>
<p>io4 : inout BIT; -- io4</p>
<p>io5 : inout BIT; -- io5</p>
<p>io6 : inout BIT; -- io6</p>
<p>io7 : inout BIT; -- io7</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END ram;</p>
<p>-- Architecture Declaration</p>
<p>ARCHITECTURE VST OF ram IS</p>
<p>COMPONENT a2_y</p>
<p>port (</p>
<p>i0 : in BIT; -- i0</p>
<p>i1 : in BIT; -- i1</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT mc</p>
<p>port (</p>
<p>x : in BIT; -- x</p>
<p>res : in BIT; -- res</p>
<p>rowsel : in BIT; -- rowsel</p>
<p>wren : in BIT; -- wren</p>
<p>y : out BIT; -- y</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>COMPONENT p1_y</p>
<p>port (</p>
<p>i : in BIT; -- i</p>
<p>t : out BIT; -- t</p>
<p>vdd : in BIT; -- vdd</p>
<p>vss : in BIT -- vss</p>
<p>);</p>
<p>END COMPONENT;</p>
<p>SIGNAL in0 : BIT; -- in0</p>
<p>SIGNAL in1 : BIT; -- in1</p>
<p>SIGNAL in2 : BIT; -- in2</p>
<p>SIGNAL in3 : BIT; -- in3</p>
<p>SIGNAL in4 : BIT; -- in4</p>
<p>SIGNAL in5 : BIT; -- in5</p>
<p>SIGNAL in6 : BIT; -- in6</p>
<p>SIGNAL in7 : BIT; -- in7</p>
<p>SIGNAL q0 : BIT; -- q0</p>
<p>SIGNAL q1 : BIT; -- q1</p>
<p>SIGNAL q2 : BIT; -- q2</p>
<p>SIGNAL q3 : BIT; -- q3</p>
<p>SIGNAL q4 : BIT; -- q4</p>
<p>SIGNAL q5 : BIT; -- q5</p>
<p>SIGNAL q6 : BIT; -- q6</p>
<p>SIGNAL q7 : BIT; -- q7</p>
<p>SIGNAL wren : BIT; -- wren</p>
<p>BEGIN</p>
<p>and1 : a2_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => wren,</p>
<p>i1 => cs,</p>
<p>i0 => rws);</p>
<p>bufi7 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in7,</p>
<p>i => io7);</p>
<p>bufi6 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in6,</p>
<p>i => io6);</p>
<p>bufi5 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in5,</p>
<p>i => io5);</p>
<p>bufi4 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in4,</p>
<p>i => io4);</p>
<p>bufi3 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in3,</p>
<p>i => io3);</p>
<p>bufi2 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in2,</p>
<p>i => io2);</p>
<p>bufi1 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in1,</p>
<p>i => io1);</p>
<p>bufi0 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => in0,</p>
<p>i => io0);</p>
<p>mc07 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc06 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc05 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc04 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc03 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc02 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc01 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc00 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(0));</p>
<p>mc17 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc16 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc15 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc14 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc13 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc12 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc11 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc10 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(1));</p>
<p>mc27 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc26 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc25 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc24 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc23 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc22 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc21 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc20 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(2));</p>
<p>mc37 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc36 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc35 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc34 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc33 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc32 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc31 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc30 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(3));</p>
<p>mc47 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc46 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc45 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc44 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc43 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc42 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc41 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc40 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(4));</p>
<p>mc57 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc56 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc55 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc54 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc53 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc52 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc51 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc50 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(5));</p>
<p>mc67 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc66 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc65 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc64 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc63 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc62 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc61 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc60 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(6));</p>
<p>mc77 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc76 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc75 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc74 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc73 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc72 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc71 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc70 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(7));</p>
<p>mc87 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc86 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc85 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc84 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc83 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc82 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc81 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc80 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(8));</p>
<p>mc97 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc96 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc95 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc94 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc93 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc92 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc91 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc90 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(9));</p>
<p>mc107 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc106 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc105 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc104 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc103 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc102 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc101 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc100 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(10));</p>
<p>mc117 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc116 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc115 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc114 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc113 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc112 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc111 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc110 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(11));</p>
<p>mc127 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc126 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc125 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc124 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc123 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc122 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc121 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc120 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(12));</p>
<p>mc137 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc136 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc135 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc134 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc133 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc132 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc131 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc130 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(13));</p>
<p>mc147 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc146 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc145 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc144 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc143 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc142 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc141 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc140 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(14));</p>
<p>mc157 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q7,</p>
<p>wren => res,</p>
<p>rowsel => in7,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc156 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q6,</p>
<p>wren => res,</p>
<p>rowsel => in6,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc155 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q5,</p>
<p>wren => res,</p>
<p>rowsel => in5,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc154 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q4,</p>
<p>wren => res,</p>
<p>rowsel => in4,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc153 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q3,</p>
<p>wren => res,</p>
<p>rowsel => in3,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc152 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q2,</p>
<p>wren => res,</p>
<p>rowsel => in2,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc151 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q1,</p>
<p>wren => res,</p>
<p>rowsel => in1,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>mc150 : mc</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>y => q0,</p>
<p>wren => res,</p>
<p>rowsel => in0,</p>
<p>res => wren,</p>
<p>x => c(15));</p>
<p>bufo7 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io7,</p>
<p>i => q7);</p>
<p>bufo6 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io6,</p>
<p>i => q6);</p>
<p>bufo5 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io5,</p>
<p>i => q5);</p>
<p>bufo4 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io4,</p>
<p>i => q4);</p>
<p>bufo3 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io3,</p>
<p>i => q3);</p>
<p>bufo2 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io2,</p>
<p>i => q2);</p>
<p>bufo1 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io1,</p>
<p>i => q1);</p>
<p>bufo0 : p1_y</p>
<p>PORT MAP (</p>
<p>vss => vss,</p>
<p>vdd => vdd,</p>
<p>t => io0,</p>
<p>i => q0);</p>
<p>end VST;</p>
</font>
<b><font size=+1>Maintainers and Authors :</font></b>
<p>LCD Driver development team
<p>current members:
<ul>
<li>
<a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li>
<li>
<a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li>
</ul>
<p>
<b><font size=+1>Mailing-list:</font></b>
<ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul>
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<td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td>
<td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td>
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