Subversion Repositories mem_ctrl

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<b><font face="Helvetica, Arial"><font color="#BF0000"><font size=+2>Project Name: 
WISHBONE Memory Controller IP Core</font></font></font></b> 
<p><font size=-1>(See change Log at bottom of page for changes/updates)</font>
<br>&nbsp;
<p><u><font size=+1>Description</font></u>
<p>This is a advanced Memory Controller intended for embedded applications. Some 
  of the features are: 
<ul>
  <li>SDRAM, SSRAM, FLASH, ROM and many other devices supported</li>
  <li>8 Chip selects, each uniquely programmable</li>
  <li>Flexible timing to accommodate a variety of memory devices</li>
  <li>Burst transfers and burst termination</li>
  <li>Performance optimization by leaving active rows open</li>
  <li>Default boot sequence support</li>
  <li>Dynamic bus sizing for reading from Async. Devices</li>
  <li>Byte parity Generation and Checking</li>
  <li>Multi Master memory bus support</li>
  <li>Industry standard WISHBONE SoC host interface</li>
  <li>Up to 8 * 128 Mbyte memory size</li>
  <li>Supports Power Down Mode </li>
</ul>
<p><u><font size=+1>Status</font></u> 
<ul>
  <li> 8/2/2001 I have fixed various bugs and made many small changes and am still 
    trying to improve and debug the memory controller further.</li>
  <li>New Directory Structure ! We have agreed on a common directory structure 
    at OpenCores.</li>
  <li><font color="#FF0000">PLEASE HELP</font>: I'm looking for people to help 
    me verify the core</li>
  <li> I will post a message to cores@opencores.org_NOSPAM each time I have an 
    update </li>
</ul>
<p><u><font size="+1">Downloading</font></u>
<p>To get a tared and gziped snapshot from CVS click <a href="http://www.opencores.org/cgi-bin/cvsget.cgi?module=mem_ctrl">here</a>, 
  or go to the <a href="http://www.opencores.org/cvs.shtml">CVS info page</a>.</p>
<p>The latest Specification is available here: <a href="http://www.opencores.org/cgi-bin/cvsget.cgi/mem_ctrl/doc/mc_doc.pdf">mc_doc.pdf 
  (about 260K)</a></p>
<p><u><font size=+1>Author / Maintainer</font></u> 
<p>I have been doing ASIC design, verification and synthesis for over 15 years. 
  I hope you find this cores useful. Please send me a note if you intend to use 
  it&nbsp; ! 
<p>Rudolf Usselmann
<br>
  <a href="mailto:rudi@asics.ws_NOSPAM">rudi@asics.ws_NOSPAM</a> <br>
  <a href="http://www.asics.ws">www.asics.ws</a> 
<p>Feel free to send me comments, suggestions and bug reports. 
<p>&nbsp;
<p><u><font size=+1>Change Log</font></u> 
<blockquote> 8/2/2001 Many Bug Fixes and Changes, Directory Structure Update<br>
  13/5/2001 Core Done Update<br>
  19/4/2001 Updates List of Features<br>
  7/4/2001 RU Initial web page </blockquote>
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