URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [ut699rh-evab/] [leon3mp.ucf] - Rev 2

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CONFIG STEPPING="2";                            
                                
NET "clk" PERIOD = 20.000 ;                             
OFFSET = out : 37.000 : AFTER clk ;                             
OFFSET = in : 8.000 : BEFORE clk ;                              
                                
NET "pci_clk" PERIOD = 30.000 ;                         
OFFSET = OUT : 11.000 : AFTER pci_clk ;                         
OFFSET = IN : 7.000 : BEFORE pci_clk ;                          
NET pci_arb_req(0) OFFSET = IN : 10.000 : BEFORE pci_clk ;                              
NET pci_arb_req(1) OFFSET = IN : 10.000 : BEFORE pci_clk ;                              
NET pci_arb_req(2) OFFSET = IN : 10.000 : BEFORE pci_clk ;                              
NET pci_arb_req(3) OFFSET = IN : 10.000 : BEFORE pci_clk ;                              
NET pci_arb_gnt(0) OFFSET = OUT : 12.000 : AFTER pci_clk ;                              
NET pci_arb_gnt(1) OFFSET = OUT : 12.000 : AFTER pci_clk ;                              
NET pci_arb_gnt(2) OFFSET = OUT : 12.000 : AFTER pci_clk ;                              
NET pci_arb_gnt(3) OFFSET = OUT : 12.000 : AFTER pci_clk ;                              

NET "erx_clk" PERIOD = 40.000 ;                         
OFFSET = IN : 8.000 : BEFORE erx_clk ;                          
                                
NET "etx_clk" PERIOD = 40.000 ;                         
OFFSET = OUT : 15.000 : AFTER etx_clk ;                         
OFFSET = IN : 8.000 : BEFORE etx_clk ;                          

#NET  "spw_clkl" PERIOD = 20.000 ;                              

NET "core0/leon3core0/clkm" TNM_NET = "clkm";
NET "core0/leon3core0/clk2x" TNM_NET = "clk2x";
TIMESPEC "TS_clkm_clk2x" = FROM "clkm" TO "clk2x" TIG;
TIMESPEC "TS_clk2x_clkm" = FROM "clk2x" TO "clkm" TIG;

NET  "core0/leon3core0/spw.swloop.3.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
NET  "core0/leon3core0/spw.swloop.2.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
NET  "core0/leon3core0/spw.swloop.1.grspw0/rxclki_1(0)" PERIOD = 6.000 ;
NET  "core0/leon3core0/spw.swloop.0.grspw0/rxclki_1(0)" PERIOD = 6.000 ;

INST "core0/leon3core0/spw.swloop.3.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.3.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.2.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.2.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE"; 
INST "core0/leon3core0/spw.swloop.1.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.1.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.0.grspw0/rtl.grspwc0/rx.0.rx0/r.shftreg" IOB="FALSE";
INST "core0/leon3core0/spw.swloop.0.grspw0/rtl.grspwc0/rx.0.rx0/nr.shftreg(0)" IOB="FALSE"; 

NET resetn TIG;
NET pci_rst TIG;
NET pci_host TIG;
                                
# Main Device Control Inputs                            
NET "clk"                LOC =  "F18"   | IOSTANDARD = LVCMOS33 ;       # Main System Clock (Input)
NET "resetn"            LOC =  "AF5"    | IOSTANDARD = LVCMOS33 ;       # System Reset (Input)
                                
# Local Memory Signals                          
NET "address(0)"        LOC =  "AB6"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(1)"        LOC =  "AB5"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(2)"        LOC =  "AC3"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(3)"        LOC =  "AC2"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(4)"        LOC =  "Y11"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(5)"        LOC =  "AA11"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(6)"        LOC =  "AD2"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(7)"        LOC =  "AD1"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(8)"        LOC =  "Y14"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(9)"        LOC =  "AA13"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(10)"       LOC =  "AC5"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(11)"       LOC =  "AC4"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(12)"       LOC =  "AF1"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(13)"       LOC =  "AE1"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(14)"       LOC =  "AA9"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(15)"       LOC =  "AA8"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(16)"       LOC =  "Y13"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(17)"       LOC =  "Y12"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(18)"       LOC =  "AE3"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(19)"       LOC =  "AE2"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(20)"       LOC =  "AD6"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(21)"       LOC =  "AD5"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(22)"       LOC =  "AC7"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(23)"       LOC =  "AB8"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(24)"       LOC =  "Y16"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(25)"       LOC =  "AA15"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(26)"       LOC =  "AE4"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
NET "address(27)"       LOC =  "AD4"    | IOSTANDARD = LVCMOS33 ;       # Local Memory Address Bus
                                
NET "data(0)"           LOC =  "AJ22"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(1)"           LOC =  "AJ21"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(2)"           LOC =  "AC15"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(3)"           LOC =  "AB15"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(4)"           LOC =  "AG22"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(5)"           LOC =  "AH22"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(6)"           LOC =  "AL14"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(7)"           LOC =  "AK14"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(8)"           LOC =  "AG21"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(9)"           LOC =  "AF20"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(10)"          LOC =  "AF14"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(11)"          LOC =  "AG13"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(12)"          LOC =  "AE21"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(13)"          LOC =  "AF21"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(14)"          LOC =  "AP15"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(15)"          LOC =  "AN15"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(16)"          LOC =  "AA25"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(17)"          LOC =  "AA26"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(18)"          LOC =  "AE32"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(19)"          LOC =  "AD32"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(20)"          LOC =  "AC28"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(21)"          LOC =  "AB28"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(22)"          LOC =  "AD30"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(23)"          LOC =  "AD31"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(24)"          LOC =  "AG32"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(25)"          LOC =  "AG33"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(26)"          LOC =  "AF33"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(27)"          LOC =  "AF34"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(28)"          LOC =  "AE29"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(29)"          LOC =  "AD29"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(30)"          LOC =  "AF31"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
NET "data(31)"          LOC =  "AE31"   | IOSTANDARD = LVCMOS33 ;       # Local Memory Data Bus
                                
NET "cb(0)"             LOC =  "AA23"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(1)"             LOC =  "AA24"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(2)"             LOC =  "AJ34"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(3)"             LOC =  "AH34"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(4)"             LOC =  "AD27"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(5)"             LOC =  "AC27"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(6)"             LOC =  "AB25"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
NET "cb(7)"             LOC =  "AB26"   | IOSTANDARD = LVCMOS33 ;       # EDAC Check bit (bi-direct)
                                
# PROM and I/O bus Control Signals                              
NET "writen"            LOC =  "AG30"   | IOSTANDARD = LVCMOS33 ;       # PROM/ I/O Space Write Enable (Output)
NET "oen"               LOC =  "AG31"   | IOSTANDARD = LVCMOS33 ;       # PROM I/O Space Output Enable (Output)
NET "iosn"              LOC =  "AH32"   | IOSTANDARD = LVCMOS33 ;       # I/O Space Chip Select (Output)
                                
NET "romsn(0)"          LOC =  "AH33"   | IOSTANDARD = LVCMOS33 ;       # PROM Chip Select bank 0 (Output)
NET "romsn(1)"          LOC =  "AC25"   | IOSTANDARD = LVCMOS33 ;       # PROM Chip Select bank 1 (Output)
                                
# SRAM Control Signals                          
NET "rwen(0)"           LOC =  "AK31"   | IOSTANDARD = LVCMOS33 ;       # SRAM Write Enable Byte 0 (Output)
NET "rwen(1)"           LOC =  "AK32"   | IOSTANDARD = LVCMOS33 ;       # SRAM Write Enable Byte 1 (Output)
NET "rwen(2)"           LOC =  "AK33"   | IOSTANDARD = LVCMOS33 ;       # SRAM Write Enable Byte 2 (Output)
NET "rwen(3)"           LOC =  "AK34"   | IOSTANDARD = LVCMOS33 ;       # SRAM Write Enable Byte 3 (Output)
                                
NET "ramoen(0)"         LOC =  "AB22"   | IOSTANDARD = LVCMOS33 ;       # SRAM Output Enable bank 0
NET "ramoen(1)"         LOC =  "AB23"   | IOSTANDARD = LVCMOS33 ;       # SRAM Output Enable bank 1
NET "ramoen(2)"         LOC =  "AL33"   | IOSTANDARD = LVCMOS33 ;       # SRAM Output Enable bank 2
NET "ramoen(3)"         LOC =  "AL34"   | IOSTANDARD = LVCMOS33 ;       # SRAM Output Enable bank 3
NET "ramoen(4)"         LOC =  "AM31"   | IOSTANDARD = LVCMOS33 ;       # SRAM Output Enable bank 4
                                
NET "ramsn(0)"          LOC =  "AM32"   | IOSTANDARD = LVCMOS33 ;       # SRAM Chip Enable bank 0
NET "ramsn(1)"          LOC =  "AM33"   | IOSTANDARD = LVCMOS33 ;       # SRAM Chip Enable bank 1
NET "ramsn(2)"          LOC =  "AJ31"   | IOSTANDARD = LVCMOS33 ;       # SRAM Chip Enable bank 2
NET "ramsn(3)"          LOC =  "AJ32"   | IOSTANDARD = LVCMOS33 ;       # SRAM Chip Enable bank 3
NET "ramsn(4)"          LOC =  "AH30"   | IOSTANDARD = LVCMOS33 ;       # SRAM Chip Enable bank 4
                                
# SDRAM Interface Signals                               
NET "sdclk"             LOC =  "AL3"    | IOSTANDARD = LVCMOS33 ;       # SDRAM CLK (Output)
NET "pllref"            LOC =  "H17"    | IOSTANDARD = LVCMOS33 ;       # feedback clock for SDRAM (Input)
NET "sdrasn"            LOC =  "AB13"   | IOSTANDARD = LVCMOS33 ;       # SDRAM RAS (Output)
NET "sdcasn"            LOC =  "AB12"   | IOSTANDARD = LVCMOS33 ;       # SDRAM CAS (Output)
NET "sdwen"             LOC =  "AM2"    | IOSTANDARD = LVCMOS33 ;       # SDRAM WREN (Output)
                                
NET "sdcsn(0)"          LOC =  "AM1"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Chip Select bank 0
NET "sdcsn(1)"          LOC =  "AG8"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Chip Select bank 1
                                
NET "sdcke(0)"          LOC =  "AG7"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Clock Enable bank 0
NET "sdcke(1)"          LOC =  "AM3"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Clock Enable bank 1
                                
NET "sddqm(0)"          LOC =  "AC10"   | IOSTANDARD = LVCMOS33 ;       # SDRAM Data Mask (Output)
NET "sddqm(1)"          LOC =  "AB10"   | IOSTANDARD = LVCMOS33 ;       # SDRAM Data Mask (Output)
NET "sddqm(2)"          LOC =  "AK3"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Data Mask (Output)
NET "sddqm(3)"          LOC =  "AK2"    | IOSTANDARD = LVCMOS33 ;       # SDRAM Data Mask (Output)
                                
# Memory Bus Status Signals                             
NET "read"              LOC =  "AJ2"    | IOSTANDARD = LVCMOS33 ;       # Read cycle indicator ? Function
NET "bexcn"             LOC =  "AC9"    | IOSTANDARD = LVCMOS33 ;       # Bus Error Exception (Input)
NET "brdyn"             LOC =  "AG3"    | IOSTANDARD = LVCMOS33 ;       # Bus Ready (Input)
                                
# System Status Signals                         
NET "errorn"            LOC =  "AG5"    | IOSTANDARD = LVCMOS33 ;       # Processor Error (Output)
NET "wdogn"             LOC =  "AD7"    | IOSTANDARD = LVCMOS33 ;       # Timer 4 Watchdog timeout (output)
                                
                                
# CAN BUS 1                             
NET "can_rxd(0)"        LOC =  "K34"    | IOSTANDARD = LVCMOS33 ;       # CAN bus Receive data (Input)
NET "can_txd(0)"        LOC =  "J34"    | IOSTANDARD = LVCMOS33 ;       # CAN bus Transmit data (Output)
                                
# CAN BUS 2                             
NET "can_rxd(1)"        LOC =  "N30"    | IOSTANDARD = LVCMOS33 ;       # CAN bus Receive data (Input)
NET "can_txd(1)"         LOC =  "N29"   | IOSTANDARD = LVCMOS33 ;       # CAN bus Transmit data (Output)
                                
                                
# DSU Debug Control Signals                             
NET "dsuact"            LOC =  "R24"    | IOSTANDARD = LVCMOS33 ;       # DSU Active (Output)
NET "dsubre"            LOC =  "H32"    | IOSTANDARD = LVCMOS33 ;       # DSU Break (Input)
NET "dsuen"             LOC =  "J32"    | IOSTANDARD = LVCMOS33 ;       # DSU Enable (Input)
                                
# DSU Debug UART                                
NET "dsurx"             LOC =  "M32"    | IOSTANDARD = LVCMOS33 ;       # DSU Receive UART (Input)
NET "dsutx"             LOC =  "M33"    | IOSTANDARD = LVCMOS33 ;       # DSU Transmit UART (Transmit)
                                
                                
# Ethernet Signals                              
NET "emdc"              LOC =  "N23"    | IOSTANDARD = LVCMOS33 ;       # (EMCLK) Ethernet PHY Clock (Output)
                                
NET "emdio"             LOC =  "N22"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface DIO (bi-direct)
                                
NET "erx_clk"           LOC =  "AK18"   | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receive Clock (Input)
NET "erx_col"           LOC =  "H29"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Collision Detect (Input)
NET "erx_crs"            LOC =  "L30"   | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Carrier Sense (Input)
NET "erx_dv"            LOC =  "H34"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Data Valid (Input)
NET "erx_er"            LOC =  "J31"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receiption Error (Input)
                                
NET "erxd(0)"           LOC =  "J27"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receive Data (Input)
NET "erxd(1)"           LOC =  "K27"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receive Data (Input)
NET "erxd(2)"           LOC =  "M25"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receive Data (Input)
NET "erxd(3)"           LOC =  "M26"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Receive Data (Input)
                                
NET "etx_clk"           LOC =  "AH19"   | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Clock (Input)
NET "etx_en"            LOC =  "C33"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Enable (Output)
NET "etx_er"            LOC =  "R22"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Error (Output)
                                
NET "etxd(0)"           LOC =  "H27"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Data (Output)
NET "etxd(1)"           LOC =  "H28"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Data (Output)
NET "etxd(2)"           LOC =  "C32"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Data (Output)
NET "etxd(3)"           LOC =  "D32"    | IOSTANDARD = LVCMOS33 ;       # Ethernet Media Interface Transmit Data (Output)
                                
NET "gpio(0)"           LOC =  "G30"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(1)"           LOC =  "G31"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(2)"           LOC =  "J29"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(3)"           LOC =  "J30"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(4)"           LOC =  "E32"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(5)"           LOC =  "E33"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(6)"           LOC =  "N25"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(7)"           LOC =  "P26"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(8)"           LOC =  "P22"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(9)"           LOC =  "R21"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(10)"          LOC =  "F33"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(11)"          LOC =  "F34"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(12)"          LOC =  "K28"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(13)"          LOC =  "K29"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(14)"          LOC =  "G32"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
NET "gpio(15)"          LOC =  "G33"    | IOSTANDARD = LVCMOS33 ;       # General Purpose I/O
                                
                                
# PCI Signals                           
NET "pci_ad(0)"         LOC =  "N4"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(1)"         LOC =  "P4"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(2)"         LOC =  "N3"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(3)"         LOC =  "N2"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(4)"         LOC =  "R8"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(5)"         LOC =  "T8"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(6)"         LOC =  "R7"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(7)"         LOC =  "R6"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(8)"         LOC =  "P2"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(9)"         LOC =  "P1"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(10)"        LOC =  "R4"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(11)"        LOC =  "T4"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(12)"        LOC =  "R3"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(13)"        LOC =  "R2"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(14)"        LOC =  "R1"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(15)"        LOC =  "T1"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(16)"        LOC =  "T6"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(17)"        LOC =  "T5"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(18)"        LOC =  "T3"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(19)"        LOC =  "U3"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(20)"        LOC =  "U8"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(21)"        LOC =  "U7"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(22)"        LOC =  "U2"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(23)"        LOC =  "U1"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(24)"        LOC =  "U12"    |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(25)"        LOC =  "U11"    |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(26)"        LOC =  "U10"    |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(27)"        LOC =  "V10"    |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(28)"        LOC =  "U6"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(29)"        LOC =  "U5"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(30)"        LOC =  "V3"     |  BYPASS       ;       # PCI Address/Data Bus
NET "pci_ad(31)"        LOC =  "V2"     |  BYPASS       ;       # PCI Address/Data Bus
                                
                                
NET "pci_clk"           LOC =  "AD16"           ;       # PCI Bus Clock (Input)
                                
NET "pci_cbe(0)"        LOC =  "V9"     |  BYPASS       ;       # PCI Bus Command Byte Enable
NET "pci_cbe(1)"        LOC =  "V8"     |  BYPASS       ;       # PCI Bus Command Byte Enable
NET "pci_cbe(2)"        LOC =  "V5"     |  BYPASS       ;       # PCI Bus Command Byte Enable
NET "pci_cbe(3)"        LOC =  "V4"     |  BYPASS       ;       # PCI Bus Command Byte Enable
                                
NET "pci_devsel"        LOC =  "AA5"    |  BYPASS | PULLUP      ;       # PCI Bus Device Select (bi-direct)
NET "pci_frame"         LOC =  "AA4"    |  BYPASS | PULLUP      ;       # PCI Bus Frame (bi-direct)
NET "pci_gnt"           LOC =  "AA1"            ;       # PCI Bus Grant (Input)
NET "pci_host"          LOC =  "Y1"     |  BYPASS | PULLUP      ;       # PCI Bus Host Enable (Input)
NET "pci_idsel"         LOC =  "AB3" | PULLUP           ;       # PCI
NET "pci_irdy"          LOC =  "AA3"    |  BYPASS | PULLUP      ;       # PCI Bus Initiator Ready (bi-direct)
NET "pci_par"           LOC =  "AB2"    |  BYPASS       ;       # PCI Bus Parity (bi-direct)
#NET pci_serr                   ;       # PCI bus System Error, had to comment out due to logic trimming (found as not implemented in grlib doc)
#NET pci_lock                   ;       # PCI bus System Lockn, had to comment out due to logic trimming
NET "pci_perr"          LOC =  "AB1"    |  BYPASS | PULLUP      ;       # PCI Bus Parity Error (Input)
NET "pci_req"           LOC =  "AA6"            ;       # PCI Bus Request (Output)
NET "pci_rst"           LOC =  "Y6" | PULLUP            ;       # PCI Bus Reset (Input)
NET "pci_stop"          LOC =  "Y8"     |  BYPASS | PULLUP      ;       # PCI Bus Stop (bi-direct)
NET "pci_trdy"          LOC =  "Y7"     |  BYPASS | PULLUP      ;       # PCI Bus Target Ready (bi-direct)
NET "pci_arb_gnt(0)"            LOC =  "E29" | FAST             ;       # PCI Bus arbiter grant 0
NET "pci_arb_gnt(1)"            LOC =  "L26" | FAST             ;       # PCI Bus arbiter grant 1
NET "pci_arb_gnt(2)"            LOC =  "B33" | FAST             ;       # PCI Bus arbiter grant 2
NET "pci_arb_gnt(3)"            LOC =  "F31" | FAST             ;       # PCI Bus arbiter grant 3
NET "pci_arb_req(0)"            LOC =  "D29" | PULLUP           ;       # PCI Bus arbiter request 0
NET "pci_arb_req(1)"            LOC =  "L25" | PULLUP           ;       # PCI Bus arbiter request 1
NET "pci_arb_req(2)"            LOC =  "B32" | PULLUP           ;       # PCI Bus arbiter request 2
NET "pci_arb_req(3)"            LOC =  "E31" | PULLUP           ;       # PCI Bus arbiter request 3
                                
                                
# General Purpose UART                          
NET "rxd1"              LOC =  "L33"    | IOSTANDARD = LVCMOS33 ;       # UART Receive data (Input)
NET "txd1"              LOC =  "L34"    | IOSTANDARD = LVCMOS33 ;       # UART Transmit data (Output)
                                
                                
# SpaceWire Interface                           
#NET "spw_clk"          LOC =  "C19"            ;       # SpaceWire Transmit Clock (Input)p
NET "spw_clkp"          LOC =  "C19"            ;       # SpaceWire Transmit Clock (Input)p
NET "spw_clkn"          LOC =  "C18"            ;       # SpaceWire Transmit Clock (Input)n
                                
# SpaceWire Port 1                              
NET "spw_rxdp(0)"       LOC =  "T23" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS P
NET "spw_rxdn(0)"       LOC =  "U23" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS N
NET "spw_rxsp(0)"       LOC =  "R26" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS P
NET "spw_rxsn(0)"       LOC =  "T26" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS N
NET "spw_txdp(0)"       LOC =  "T24"            ;       # SpaceWire Transmit Data LVDS P
NET "spw_txdn(0)"       LOC =  "T25"            ;       # SpaceWire Transmit Data LVDS N
NET "spw_txsp(0)"       LOC =  "R27"            ;       # SpaceWire Transmit Strobe LVDS P
NET "spw_txsn(0)"       LOC =  "R28"            ;       # SpaceWire Transmit Strobe LVDS N
                                
# SpaceWire Port 2                              
NET "spw_rxdp(1)"       LOC =  "T29" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS P
NET "spw_rxdn(1)"       LOC =  "T30" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS N
NET "spw_rxsp(1)"       LOC =  "T33" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS P
NET "spw_rxsn(1)"       LOC =  "T34" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS N
NET "spw_txdp(1)"       LOC =  "U26"            ;       # SpaceWire Transmit Data LVDS P
NET "spw_txdn(1)"       LOC =  "U27"            ;       # SpaceWire Transmit Data LVDS N
NET "spw_txsp(1)"       LOC =  "U30"            ;       # SpaceWire Transmit Strobe LVDS P
NET "spw_txsn(1)"       LOC =  "U31"            ;       # SpaceWire Transmit Strobe LVDS N
                                
# SpaceWire Port 3                              
NET "spw_rxdp(2)"       LOC =  "V33" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS P
NET "spw_rxdn(2)"       LOC =  "V34" | IOBDELAY="NONE"          ;       # SpaceWire Receive Data LVDS N
NET "spw_rxsp(2)"       LOC =  "U32" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS P
NET "spw_rxsn(2)"       LOC =  "U33" | IOBDELAY="NONE"          ;       # SpaceWire Receive Strobe LVDS N
NET "spw_txdp(2)"       LOC =  "V25"            ;       # SpaceWire Transmit Data LVDS P
NET "spw_txdn(2)"       LOC =  "U25"            ;       # SpaceWire Transmit Data LVDS N
NET "spw_txsp(2)"       LOC =  "V28"            ;       # SpaceWire Transmit Strobe LVDS P
NET "spw_txsn(2)"       LOC =  "V29"            ;       # SpaceWire Transmit Strobe LVDS N
                                
# SpaceWire Port 4                              
NET "spw_rxdp(3)"       LOC =  "AB32" | IOBDELAY="NONE"         ;       # SpaceWire Receive Data LVDS P
NET "spw_rxdn(3)"       LOC =  "AB33" | IOBDELAY="NONE"         ;       # SpaceWire Receive Data LVDS N
NET "spw_rxsp(3)"       LOC =  "AA33" | IOBDELAY="NONE"         ;       # SpaceWire Receive Strobe LVDS P
NET "spw_rxsn(3)"       LOC =  "AA34" | IOBDELAY="NONE"         ;       # SpaceWire Receive Strobe LVDS N
NET "spw_txdp(3)"       LOC =  "AB31"           ;       # SpaceWire Transmit Data LVDS P
NET "spw_txdn(3)"       LOC =  "AA31"           ;       # SpaceWire Transmit Data LVDS N
NET "spw_txsp(3)"       LOC =  "Y27"            ;       # SpaceWire Transmit Strobe LVDS P
NET "spw_txsn(3)"       LOC =  "Y28"            ;       # SpaceWire Transmit Strobe LVDS N
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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [ut699rh-evab/] [leon3mp.ucf] - Rev 2
