URL https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced

[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [xilinx-ml507-xc5vfx70t/] [leon3mp.ucf] - Rev 2

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NET sram_clk FEEDBACK = 1.0 NET sram_clk_fb;
NET "clkm"              TNM_NET = "clkm";
NET "clkml"             TNM_NET = "clkml";
TIMESPEC "TS_clkm_clkml" = FROM "clkm" TO "clkml" TIG;
TIMESPEC "TS_clkml_clkm" = FROM "clkml" TO "clkm" TIG;
#NET "lock"  TIG;

NET phy_tx_data(*) TNM = gtxphypads;
NET "egtx_clk"  TNM_NET = "egtx_clk";
TIMESPEC "TS_clkm_egtx_clk" = FROM "clkm" TO "egtx_clk" TIG;
TIMESPEC "TS_egtx_clk_clkm" = FROM "egtx_clk" TO "clkm" TIG;
#TIMESPEC "TSGTXOUT" = FROM "egtx_clk" TO "gtxphypads" 4.3 ns;
#TIMESPEC "TSGRXIN" = FROM "gtxphypads" TO "eth1_e1_m1000_u0_rxclk" 10 ns;
NET clk_100 period = 10.000 ;

NET clk_200 period = 5.000;

#NET "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/dqsclk(*)" TNM_NET = "dqsclk"; 
#TIMEGRP "dqsclk_rise" = FALLING "dqsclk";
#TIMEGRP "clkml_rise" = RISING "clkml";
#TIMESPEC "TS_dqsclk_clkml_rise" = FROM "dqsclk_rise" TO "clkml_rise" 3.500;

INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.0.u" LOC = "IDELAYCTRL_X0Y0";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.1.u" LOC = "IDELAYCTRL_X0Y1";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl.2.u" LOC = "IDELAYCTRL_X0Y5";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[0].u" LOC = "IDELAYCTRL_X0Y0";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[1].u" LOC = "IDELAYCTRL_X0Y1";
INST "ddrsp0.ddrc0/ddr_phy0/ddr_phy0/xc4v.ddr_phy0/idelctrl[2].u" LOC = "IDELAYCTRL_X0Y5";

NET sys_rst_in PULLUP;
NET sys_rst_in TIG;

#NET  AUDIO_BIT_CLK        LOC="AF18";  # Bank 4, Vcco=3.3V, No DCI    
#NET  AUDIO_SDATA_IN       LOC="AE18";  # Bank 4, Vcco=3.3V, No DCI    
#NET  AUDIO_SDATA_OUT      LOC="AG16";  # Bank 4, Vcco=3.3V, No DCI    
#NET  AUDIO_SYNC           LOC="AF19";  # Bank 4, Vcco=3.3V, No DCI    
NET  bus_error(0)         LOC="F6" | IOSTANDARD = LVDCI_33;    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  bus_error(1)         LOC="T10" | IOSTANDARD = LVDCI_33;   # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_addr(22)  LOC="AE12";  # Bank 2, Vcco=3.3V      
NET  sram_flash_addr(23)  LOC="AE13";  # Bank 2, Vcco=3.3V      
NET  clk_27               LOC="AG18";  # Bank 4, Vcco=3.3V, No DCI      
NET  clk_33               LOC="AH17";  # Bank 4, Vcco=3.3V, No DCI      
NET  clk_200_n            LOC="K19" | IOSTANDARD = LVDS_25;   # Bank 3, Vcco=2.5V, No DCI      
NET  clk_200_p            LOC="L19" | IOSTANDARD = LVDS_25;   # Bank 3, Vcco=2.5V, No DCI      
#NET  CLKBUF_Q0_N          LOC="H3";    # Bank 116, MGTREFCLKN_116, GTP_DUAL_X0Y4
#NET  CLKBUF_Q0_P          LOC="H4";    # Bank 116, MGTREFCLKP_116, GTP_DUAL_X0Y4
#NET  CLKBUF_Q1_N          LOC="J19";   # Bank 3, Vcco=2.5V, No DCI      
#NET  CLKBUF_Q1_P          LOC="K18";   # Bank 3, Vcco=2.5V, No DCI      
#NET  CPLD_IO_1            LOC="W10";   # Bank 18, Vcco=3.3V, No DCI      
#NET  CPU_TCK              LOC="E6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  CPU_TDO              LOC="E7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  CPU_TMS              LOC="U10";   # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  CPU_TRST             LOC="V10";   # Bank 18, Vcco=3.3V, No DCI      
NET  ddr_ad(0)            LOC="L30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(1)            LOC="M30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(2)            LOC="N29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(3)            LOC="P29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(4)            LOC="K31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(5)            LOC="L31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(6)            LOC="P31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(7)            LOC="P30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(8)            LOC="M31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(9)            LOC="R28" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ad(10)           LOC="J31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(11)           LOC="R29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(12)           LOC="T31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ad(13)           LOC="H29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ddr_ba(0)            LOC="G31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_ba(1)            LOC="J30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
# REMOVED *** NET  ddr_ba(2)            LOC="R31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_casb             LOC="E31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_cke(0)           LOC="T28" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_cke(1)           LOC="U30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_clkb(0)          LOC="AJ29" | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_clk(0)           LOC="AK29" | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_clkb(1)          LOC="F28" | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_clk(1)           LOC="E28" | IOSTANDARD = SSTL18_I; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_csb(0)           LOC="L29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_csb(1)           LOC="J29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(0)            LOC="AF30" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(1)            LOC="AK31" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(2)            LOC="AF31" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(3)            LOC="AD30" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(4)            LOC="AJ30" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(5)            LOC="AF29" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(6)            LOC="AD29" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(7)            LOC="AE29" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(8)            LOC="AH27" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(9)            LOC="AF28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(10)           LOC="AH28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(11)           LOC="AA28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(12)           LOC="AG25" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(13)           LOC="AJ26" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(14)           LOC="AG28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(15)           LOC="AB28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(16)           LOC="AC28" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(17)           LOC="AB25" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(18)           LOC="AC27" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(19)           LOC="AA26" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(20)           LOC="AB26" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(21)           LOC="AA24" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(22)           LOC="AB27" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(23)           LOC="AA25" | IOSTANDARD = SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(24)           LOC="AC29" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(25)           LOC="AB30" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(26)           LOC="W31" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(27)           LOC="V30" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(28)           LOC="AC30" | IOSTANDARD = SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(29)           LOC="W29" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(30)           LOC="V27" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(31)           LOC="W27" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(32)           LOC="V29" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(33)           LOC="Y27" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(34)           LOC="Y26" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(35)           LOC="W24" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(36)           LOC="V28" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(37)           LOC="W25" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(38)           LOC="W26" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(39)           LOC="V24" | IOSTANDARD = SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(40)           LOC="R24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(41)           LOC="P25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(42)           LOC="N24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(43)           LOC="P26" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(44)           LOC="T24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(45)           LOC="N25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(46)           LOC="P27" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(47)           LOC="N28" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(48)           LOC="M28" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(49)           LOC="L28" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(50)           LOC="F25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(51)           LOC="H25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(52)           LOC="K27" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(53)           LOC="K28" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(54)           LOC="H24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(55)           LOC="G26" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(56)           LOC="G25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(57)           LOC="M26" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(58)           LOC="J24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(59)           LOC="L26" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(60)           LOC="J27" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(61)           LOC="M25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(62)           LOC="L25" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dq(63)           LOC="L24" | IOSTANDARD = SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(0)            LOC="AJ31" | IOSTANDARD = SSTL18_I;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(1)            LOC="AE28" | IOSTANDARD = SSTL18_I;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(2)            LOC="Y24" | IOSTANDARD = SSTL18_I;   # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(3)            LOC="Y31" | IOSTANDARD = SSTL18_I;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(4)            LOC="V25" | IOSTANDARD = SSTL18_I;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(5)            LOC="P24" | IOSTANDARD = SSTL18_I;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(6)            LOC="F26" | IOSTANDARD = SSTL18_I;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dm(7)            LOC="J25" | IOSTANDARD = SSTL18_I;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(0)          LOC="AA30" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(0)          LOC="AA29" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(1)          LOC="AK27" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(1)          LOC="AK28" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(2)          LOC="AJ27" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(2)          LOC="AK26" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(3)          LOC="AA31" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(3)          LOC="AB31" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(4)          LOC="Y29" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(4)          LOC="Y28" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(5)          LOC="E27" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(5)          LOC="E26" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(6)          LOC="G28" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(6)          LOC="H28" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsn(7)          LOC="H27" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_dqsp(7)          LOC="G27" | IOSTANDARD = DIFF_SSTL18_II; #DIFF_SSTL18_II;   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_odt(0)           LOC="F31" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_odt(1)           LOC="F30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_rasb             LOC="H30" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  DDR2_SCL             LOC="E29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  DDR2_SDA             LOC="F29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ddr_web              LOC="K29" | IOSTANDARD = SSTL18_I;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  DVI_D0               LOC="AB8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D1               LOC="AC8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D2               LOC="AN12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D3               LOC="AP12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D4               LOC="AA9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D5               LOC="AA8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D6               LOC="AM13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D7               LOC="AN13";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D8               LOC="AA10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D9               LOC="AB10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D10              LOC="AP14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_D11              LOC="AN14";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_DE               LOC="AE8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_GPIO1            LOC="N30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  DVI_H                LOC="AM12";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_RESET_B          LOC="AK6";   # Bank 18, Vcco=3.3V, No DCI
#NET  DVI_V                LOC="AM11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_XCLK_N           LOC="AL10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  DVI_XCLK_P           LOC="AL11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FAN_ALERT_B          LOC="T30";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  flash_adv_n          LOC="F13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors (FLASH_ADV_B)
#NET  FLASH_AUDIO_RESET_B  LOC="AG17";  # Bank 4, Vcco=3.3V, No DCI
NET  flash_ce             LOC="AE14";  # Bank 2, Vcco=3.3V
#NET  FLASH_CLK            LOC="N9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  flash_oen            LOC="AF14";  # Bank 2, Vcco=3.3V (FLASH_OE_B)
#NET  FLASH_WAIT           LOC="G13";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_AVDD            LOC="T18";   # Bank 0, Vcco=3.3V
#NET  FPGA_CCLK-R          LOC="N15";   # Bank 0, Vcco=3.3V
NET  sys_rst_in           LOC="E9" | IOSTANDARD = LVCMOS33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_CS_B            LOC="N22";   # Bank 0, Vcco=3.3V
#NET  FPGA_CS0_B           LOC="AF21";  # Bank 2, Vcco=3.3V
#NET  FPGA_DIFF_CLK_OUT_N  LOC="J21";   # Bank 3, Vcco=2.5V, No DCI
#NET  FPGA_DIFF_CLK_OUT_P  LOC="J20";   # Bank 3, Vcco=2.5V, No DCI
#NET  FPGA_DIN             LOC="P15";   # Bank 0, Vcco=3.3V
#NET  FPGA_DONE            LOC="M15";   # Bank 0, Vcco=3.3V
#NET  FPGA_DOUT_BUSY       LOC="AD15";  # Bank 0, Vcco=3.3V
#NET  FPGA_DX_N            LOC="W17";   # Bank 0, Vcco=3.3V
#NET  FPGA_DX_P            LOC="W18";   # Bank 0, Vcco=3.3V
#NET  FPGA_EXP_TCK         LOC="AB15";  # Bank 0, Vcco=3.3V
#NET  FPGA_EXP_TMS         LOC="AC14";  # Bank 0, Vcco=3.3V
#NET  FPGA_HSWAPEN         LOC="M23";   # Bank 0, Vcco=3.3V
#NET  FPGA_INIT_B          LOC="N14";   # Bank 0, Vcco=3.3V
#NET  FPGA_M0              LOC="AD21";  # Bank 0, Vcco=3.3V
#NET  FPGA_M1              LOC="AC22";  # Bank 0, Vcco=3.3V
#NET  FPGA_M2              LOC="AD22";  # Bank 0, Vcco=3.3V
#NET  FPGA_PROG_B          LOC="M22";   # Bank 0, Vcco=3.3V
#NET  FPGA_RDWR_B          LOC="N23";   # Bank 0, Vcco=3.3V
#NET  FPGA_ROTARY_INCA     LOC="AH30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_ROTARY_INCB     LOC="AG30";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_ROTARY_PUSH     LOC="AH29";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  rxd1                 LOC="AG15" | IOSTANDARD = LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
NET  txd1                 LOC="AG20" | IOSTANDARD = LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
NET  rxd2                 LOC="G10" | IOSTANDARD = LVCMOS33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  txd2                 LOC="F10" | IOSTANDARD = LVCMOS33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_TDI             LOC="AC15";  # Bank 0, Vcco=3.3V
#NET  FPGA_TDO             LOC="AD14";  # Bank 0, Vcco=3.3V
#NET  FPGA_V_N             LOC="V17";   # Bank 0, Vcco=3.3V
#NET  FPGA_V_P             LOC="U18";   # Bank 0, Vcco=3.3V
#NET  FPGA_VBATT           LOC="L23";   # Bank 0, Vcco=3.3V
#NET  FPGA_VREFP           LOC="V18";   # Bank 0, Vcco=3.3V
#NET  FPGA_VRN_B11         LOC="N33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  FPGA_VRN_B13         LOC="AG33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  FPGA_VRN_B17         LOC="AD31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRN_B19         LOC="N27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRN_B20         LOC="L10";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_VRN_B21         LOC="AJ25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRN_B22         LOC="AF8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_VRP_B11         LOC="M33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  FPGA_VRP_B13         LOC="AH33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  FPGA_VRP_B17         LOC="AE31";  # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRP_B19         LOC="M27";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRP_B20         LOC="L11";   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  FPGA_VRP_B21         LOC="AH25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  FPGA_VRP_B22         LOC="AE9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW1         LOC="U25";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW2         LOC="AG27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW3         LOC="AF25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW4         LOC="AF26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW5         LOC="AE27";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW6         LOC="AE26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW7         LOC="AC25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_DIP_SW8         LOC="AC24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_0           LOC="H18";   # Bank 3, Vcco=2.5V, No DCI
#NET  GPIO_LED_1           LOC="L18";   # Bank 3, Vcco=2.5V, No DCI
#NET  GPIO_LED_2           LOC="G15";   # Bank 3, Vcco=2.5V, No DCI
#NET  GPIO_LED_3           LOC="AD26";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_4           LOC="G16";   # Bank 3, Vcco=2.5V, No DCI
#NET  GPIO_LED_5           LOC="AD25";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_6           LOC="AD24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_7           LOC="AE24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_C           LOC="E8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  GPIO_LED_E           LOC="AG23";  # Bank 2, Vcco=3.3V
#NET  GPIO_LED_N           LOC="AF13";  # Bank 2, Vcco=3.3V
#NET  GPIO_LED_S           LOC="AG12";  # Bank 2, Vcco=3.3V
#NET  GPIO_LED_W           LOC="AF23";  # Bank 2, Vcco=3.3V
#NET  GPIO_SW_C            LOC="AJ6";   # Bank 18, Vcco=3.3V, No DCI
#NET  GPIO_SW_E            LOC="AK7";   # Bank 18, Vcco=3.3V, No DCI
#NET  GPIO_SW_N            LOC="U8";    # Bank 18, Vcco=3.3V, No DCI
#NET  GPIO_SW_S            LOC="V8";    # Bank 18, Vcco=3.3V, No DCI
#NET  GPIO_SW_W            LOC="AJ7";   # Bank 18, Vcco=3.3V, No DCI
NET  gpio(0)              LOC="U25"   | IOSTANDARD = LVCMOS18; #LVDCI_18;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(1)              LOC="AG27"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(2)              LOC="AF25"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(3)              LOC="AF26"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(4)              LOC="AE27"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(5)              LOC="AE26"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(6)              LOC="AC25"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  gpio(7)              LOC="AC24"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  led(0)               LOC="H18"   | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  led(1)               LOC="L18"   | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  led(2)               LOC="G15"   | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  led(3)               LOC="AD26"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  led(4)               LOC="G16"   | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  led(5)               LOC="AD25"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  led(6)               LOC="AD24"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  led(7)               LOC="AE24"  | IOSTANDARD = LVCMOS18; #LVDCI_18;  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  led(8)               LOC="E8"    | IOSTANDARD = LVCMOS33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  led(9)               LOC="AG23"  | IOSTANDARD = LVCMOS33;  # Bank 2, Vcco=3.3V
NET  led(10)              LOC="AF13"  | IOSTANDARD = LVCMOS33;  # Bank 2, Vcco=3.3V
NET  led(11)              LOC="AG12"  | IOSTANDARD = LVCMOS33;  # Bank 2, Vcco=3.3V
NET  led(12)              LOC="AF23"  | IOSTANDARD = LVCMOS33;  # Bank 2, Vcco=3.3V
NET  gpio(8)              LOC="AJ6"   | IOSTANDARD = LVCMOS33;   # Bank 18, Vcco=3.3V, No DCI
NET  gpio(9)              LOC="AK7"   | IOSTANDARD = LVCMOS33;   # Bank 18, Vcco=3.3V, No DCI
NET  gpio(10)             LOC="U8"    | IOSTANDARD = LVCMOS33;    # Bank 18, Vcco=3.3V, No DCI
NET  gpio(11)             LOC="V8"    | IOSTANDARD = LVCMOS33;    # Bank 18, Vcco=3.3V, No DCI
NET  gpio(12)             LOC="AJ7"   | IOSTANDARD = LVCMOS33;   # Bank 18, Vcco=3.3V, No DCI
#NET  HDR1_2               LOC="H33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_4               LOC="F34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_6               LOC="H34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_8               LOC="G33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_10              LOC="G32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_12              LOC="H32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_14              LOC="J32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_16              LOC="J34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_18              LOC ="L33";  # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_20              LOC="M32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_22              LOC="P34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_24              LOC="N34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_26              LOC="AA34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_28              LOC="AD32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_30              LOC="Y34";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_32              LOC="Y32";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_34              LOC="W32";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_36              LOC="AH34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_38              LOC="AE32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_40              LOC="AG32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_42              LOC="AH32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_44              LOC="AK34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_46              LOC="AK33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_48              LOC="AJ32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_50              LOC="AK32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_52              LOC="AL34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_54              LOC="AL33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_56              LOC="AM33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_58              LOC="AJ34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_60              LOC="AM32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_62              LOC="AN34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR1_64              LOC="AN33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_2_SM_8_N        LOC="K34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_4_SM_8_P        LOC="L34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_6_SM_7_N        LOC="K32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_8_SM_7_P        LOC="K33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_10_DIFF_0_N     LOC="N32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_12_DIFF_0_P     LOC="P32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_14_DIFF_1_N     LOC="R34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_16_DIFF_1_P     LOC="T33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_18_DIFF_2_N     LOC="R32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_20_DIFF_2_P     LOC="R33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_22_SM_10_N      LOC="T34";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_24_SM_10_P      LOC="U33";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_26_SM_11_N      LOC="U31";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_28_SM_11_P      LOC="U32";   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_30_DIFF_3_N     LOC="V33";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_32_DIFF_3_P     LOC="V32";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_34_SM_15_N      LOC="V34";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_36_SM_15_P      LOC="W34";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_38_SM_6_N       LOC="AA33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_40_SM_6_P       LOC="Y33";   # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_42_SM_14_N      LOC="AE34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_44_SM_14_P      LOC="AF34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_46_SM_12_N      LOC="AE33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_48_SM_12_P      LOC="AF33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_50_SM_5_N       LOC="AD34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_52_SM_5_P       LOC="AC34";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_54_SM_13_N      LOC="AB32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_56_SM_13_P      LOC="AC32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_58_SM_4_N       LOC="AB33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_60_SM_4_P       LOC="AC33";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_62_SM_9_N       LOC="AP32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
#NET  HDR2_64_SM_9_P       LOC="AN32";  # Bank 13, Vcco=2.5V or 3.3V user selectable by J20
NET  iic_scl_main         LOC="F9";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  IIC_SCL_SFP          LOC="R26";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  IIC_SCL_VIDEO        LOC="U27";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  iic_sda_main         LOC="F8";    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  IIC_SDA_SFP          LOC="U28";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  IIC_SDA_VIDEO        LOC="T29";   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ps2_keyb_clk         LOC="T26" | IOSTANDARD = LVCMOS18; #LVDCI_18;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  ps2_keyb_data        LOC="T25" | IOSTANDARD = LVCMOS18; #LVDCI_18;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET  LCD_FPGA_DB4         LOC="T9";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  LCD_FPGA_DB5         LOC="G7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  LCD_FPGA_DB6         LOC="G6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  LCD_FPGA_DB7         LOC="T11";   # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  LCD_FPGA_E           LOC="AC9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  LCD_FPGA_RS          LOC="J17";   # Bank 3, Vcco=2.5V, No DCI      
NET  LCD_FPGA_RW          LOC="AC10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  LOOPBK_114_N         LOC="AG1";   # Bank 118, MGTRXN1_118, GTP_DUAL_X0Y1
#NET  LOOPBK_114_N         LOC="AH2";   # Bank 118, MGTTXN1_118, GTP_DUAL_X0Y1
#NET  LOOPBK_114_P         LOC="AH1";   # Bank 118, MGTRXP1_118, GTP_DUAL_X0Y1
#NET  LOOPBK_114_P         LOC="AJ2";   # Bank 118, MGTTXP1_118, GTP_DUAL_X0Y1
#NET  LOOPBK_116_N         LOC="R1";    # Bank 112, MGTRXN1_112, GTP_DUAL_X0Y3
#NET  LOOPBK_116_N         LOC="T2";    # Bank 112, MGTTXN1_112, GTP_DUAL_X0Y3
#NET  LOOPBK_116_P         LOC="T1";    # Bank 112, MGTRXP1_112, GTP_DUAL_X0Y3
#NET  LOOPBK_116_P         LOC="U2";    # Bank 112, MGTTXP1_112, GTP_DUAL_X0Y3
NET  ps2_mouse_clk        LOC="R27" | IOSTANDARD = LVCMOS18; #LVDCI_18;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
NET  ps2_mouse_data       LOC="U26" | IOSTANDARD = LVCMOS18; #LVDCI_18;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
#NET  PC4_HALT_B           LOC="W9";    # Bank 18, Vcco=3.3V, No DCI      
#NET  PCIE_CLK_QO_N        LOC="AF3";   # Bank 118, MGTREFCLKN_118, GTP_DUAL_X0Y1
#NET  PCIE_CLK_QO_P        LOC="AF4";   # Bank 118, MGTREFCLKP_118, GTP_DUAL_X0Y1
#NET  PCIE_PRSNT_B_FPGA    LOC="AF24";  # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors      
#NET  PCIE_RX_N            LOC="AF1";   # Bank 118, MGTRXN0_118, GTP_DUAL_X0Y1
#NET  PCIE_RX_P            LOC="AE1";   # Bank 118, MGTRXP0_118, GTP_DUAL_X0Y1
#NET  PCIE_TX_N            LOC="AE2";   # Bank 118, MGTTXN0_118, GTP_DUAL_X0Y1
#NET  PCIE_TX_P            LOC="AD2";   # Bank 118, MGTTXP0_118, GTP_DUAL_X0Y1
NET  phy_col              LOC="B32" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  phy_crs              LOC="E34" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
#NET  PHY_INT              LOC="H20";   # Bank 3, Vcco=2.5V, No DCI      
NET  phy_mii_clk          LOC="H19" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI      
NET  phy_mii_data         LOC="H13" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI      
NET  phy_rst_n            LOC="J14" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI      
NET  phy_rx_clk           LOC="H17" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI      
NET  phy_dv               LOC="E32" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  phy_rx_data(0)       LOC="A33" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  phy_rx_data(1)       LOC="B33" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  phy_rx_data(2)       LOC="C33" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20      
NET  phy_rx_data(3)       LOC="C32" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_rx_data(4)       LOC="D32" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_rx_data(5)       LOC="C34" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_rx_data(6)       LOC="D34" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_rx_data(7)       LOC="F33" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_rx_er            LOC="E33" | IOSTANDARD = LVCMOS33;   # Bank 11, Vcco=2.5V or 3.3V user selectable by J20
NET  phy_gtx_clk          LOC="J16" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  phy_tx_clk           LOC="K17" | IOSTANDARD = LVCMOS25;   # Bank 3, Vcco=2.5V, No DCI
NET  phy_tx_en            LOC="AJ10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(0)       LOC="AF11" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(1)       LOC="AE11" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(2)       LOC="AH9" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(3)       LOC="AH10" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(4)       LOC="AG8" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(5)       LOC="AH8" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(6)       LOC="AG10" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  phy_tx_data(7)       LOC="AG11" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  phy_tx_er            LOC="AJ9" | IOSTANDARD = LVDCI_33 | FAST | DRIVE=8;   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors      
#NET  PIEZO_SPEAKER        LOC="G30" | IOSTANDARD = LVDCI_18 | FAST | DRIVE=8;   # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors      
#NET  RESERVED1            LOC="AB23";  # Bank 0, Vcco=3.3V      
#NET  RESERVED2            LOC="AC23";  # Bank 0, Vcco=3.3V      
#NET  RREF                 LOC="V4";    # Bank 112, MGTRREF_112, GTP_DUAL_X0Y3
#NET  SATA1_RX_N           LOC="Y1";    # Bank 114, MGTRXN0_114, GTP_DUAL_X0Y2
#NET  SATA1_RX_P           LOC="W1";    # Bank 114, MGTRXP0_114, GTP_DUAL_X0Y2
#NET  SATA1_TX_N           LOC="W2";    # Bank 114, MGTTXN0_114, GTP_DUAL_X0Y2
#NET  SATA1_TX_P           LOC="V2";    # Bank 114, MGTTXP0_114, GTP_DUAL_X0Y2
#NET  SATA2_RX_N           LOC="AA1";   # Bank 114, MGTRXN1_114, GTP_DUAL_X0Y2
#NET  SATA2_RX_P           LOC="AB1";   # Bank 114, MGTRXP1_114, GTP_DUAL_X0Y2
#NET  SATA2_TX_N           LOC="AB2";   # Bank 114, MGTTXN1_114, GTP_DUAL_X0Y2
#NET  SATA2_TX_P           LOC="AC2";   # Bank 114, MGTTXP1_114, GTP_DUAL_X0Y2
#NET  SATACLK_QO_N         LOC="Y3";    # Bank 114, MGTREFCLKN_114, GTP_DUAL_X0Y2
#NET  SATACLK_QO_P         LOC="Y4";    # Bank 114, MGTREFCLKP_114, GTP_DUAL_X0Y2
#NET  SFP_RX_N             LOC="H1";    # Bank 116, MGTRXN0_116, GTP_DUAL_X0Y4
#NET  SFP_RX_P             LOC="G1";    # Bank 116, MGTRXP0_116, GTP_DUAL_X0Y4
#NET  SFP_TX_DISABLE_FPGA  LOC="K24";   # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors      
#NET  SFP_TX_N             LOC="G2";    # Bank 116, MGTTXN0_116, GTP_DUAL_X0Y4
#NET  SFP_TX_P             LOC="F2";    # Bank 116, MGTTXP0_116, GTP_DUAL_X0Y4
#NET  SGMII_RX_N           LOC="P1";    # Bank 112, MGTRXN0_112, GTP_DUAL_X0Y3
#NET  SGMII_RX_P           LOC="N1";    # Bank 112, MGTRXP0_112, GTP_DUAL_X0Y3
#NET  SGMII_TX_N           LOC="N2";    # Bank 112, MGTTXN0_112, GTP_DUAL_X0Y3
#NET  SGMII_TX_P           LOC="M2";    # Bank 112, MGTTXP0_112, GTP_DUAL_X0Y3
#NET  SGMIICLK_QO_N        LOC="P3";    # Bank 112, MGTREFCLKN_112, GTP_DUAL_X0Y3
#NET  SGMIICLK_QO_P        LOC="P4";    # Bank 112, MGTREFCLKP_112, GTP_DUAL_X0Y3
#NET  SMA_DIFF_CLK_IN_N    LOC="H15";   # Bank 3, Vcco=2.5V, No DCI      
#NET  SMA_DIFF_CLK_IN_P    LOC="H14";   # Bank 3, Vcco=2.5V, No DCI      
#NET  SMA_RX_N             LOC="J1";    # Bank 116, MGTRXN1_116, GTP_DUAL_X0Y4
#NET  SMA_RX_P             LOC="K1";    # Bank 116, MGTRXP1_116, GTP_DUAL_X0Y4
#NET  SMA_TX_N             LOC="K2";    # Bank 116, MGTTXN1_116, GTP_DUAL_X0Y4
#NET  SMA_TX_P             LOC="L2";    # Bank 116, MGTTXP1_116, GTP_DUAL_X0Y4
#NET  SPI_CE_B             LOC="V9";    # Bank 18, Vcco=3.3V, No DCI      
NET  sram_adv_ld_n        LOC="H8" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_bw(2)           LOC="D10" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_bw(3)           LOC="D11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_bw(0)           LOC="J11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_bw(1)           LOC="K11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_clk_fb          LOC="AG21" | IOSTANDARD = LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI      
NET  sram_clk             LOC="G8" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_cen             LOC="J10" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(16)  LOC="N10" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(17)  LOC="E13" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(18)  LOC="E12" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(19)  LOC="L9" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(20)  LOC="M10" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors      
NET  sram_flash_data(21)  LOC="E11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(22)  LOC="F11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(23)  LOC="L8" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(24)  LOC="M8" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(25)  LOC="G12" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(26)  LOC="G11" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(27)  LOC="C13" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(28)  LOC="B13" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(29)  LOC="K9" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(30)  LOC="K8" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_data(31)  LOC="J9" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  sram_flash_dataQP0  LOC="D12" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  sram_flash_dataQP1  LOC="C12" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  sram_flash_dataQP2  LOC="H10" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  sram_flash_dataQP3  LOC="H9" | IOSTANDARD = LVDCI_33;    # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_flash_addr(0)   LOC="K12";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(1)   LOC="K13";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(2)   LOC="H23";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(3)   LOC="G23";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(4)   LOC="H12";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(5)   LOC="J12";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(6)   LOC="K22";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(7)   LOC="K23";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(8)   LOC="K14";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(9)   LOC="L14";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(10)  LOC="H22";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(11)  LOC="G22";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(12)  LOC="J15";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(13)  LOC="K16";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(14)  LOC="K21";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(15)  LOC="J22";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(16)  LOC="L16";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(17)  LOC="L15";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(18)  LOC="L20";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(19)  LOC="L21";   # Bank 1, Vcco=3.3V
NET  sram_flash_addr(20)  LOC="AE23";  # Bank 2, Vcco=3.3V
NET  sram_flash_addr(21)  LOC="AE22";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(0)   LOC="AD19";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(1)   LOC="AE19";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(2)   LOC="AE17";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(3)   LOC="AF16";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(4)   LOC="AD20";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(5)   LOC="AE21";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(6)   LOC="AE16";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(7)   LOC="AF15";  # Bank 2, Vcco=3.3V
NET  sram_flash_data(8)   LOC="AH13";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(9)   LOC="AH14";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(10)  LOC="AH19";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(11)  LOC="AH20";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(12)  LOC="AG13";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(13)  LOC="AH12";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(14)  LOC="AH22";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_data(15)  LOC="AG22";  # Bank 4, Vcco=3.3V, No DCI
NET  sram_flash_we_n      LOC="AF20";  # Bank 2, Vcco=3.3V
NET  sram_mode            LOC="A13" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  sram_oen             LOC="B12" | IOSTANDARD = LVDCI_33;   # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors

NET  mpaddr(0)         LOC="G5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(1)  LOC="N7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(2)  LOC="N5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(3)         LOC="P5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(4)         LOC="R6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(5)         LOC="M6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpaddr(6)         LOC="L6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpbrdy        LOC="H5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpce          LOC="M5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpirq         LOC="M7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpoen          LOC="N8";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpwrn          LOC="R9";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(0)        LOC="P9";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(1)        LOC="T8";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(2)        LOC="J7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(3)        LOC="H7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(4)        LOC="R7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(5)        LOC="U7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(6)        LOC="P7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(7)        LOC="P6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(8)        LOC="R8";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(9)        LOC="L5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(10)       LOC="L4";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(11)       LOC="K6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(12)       LOC="J5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(13)       LOC="T6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(14)       LOC="K7";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  mpdata(15)       LOC="J6";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors

#NET  TRC_CLK              LOC="AD9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS1E             LOC="AK9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS1O             LOC="AF10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS2E             LOC="AK8";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS2O             LOC="AF9";   # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS3              LOC="AJ11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS4              LOC="AK11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS5              LOC="AD11";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
#NET  TRC_TS6              LOC="AD10";  # Bank 22, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  usb_csn              LOC="P10" | IOSTANDARD = LVCMOS33;   # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors (USB_CS_B) 
#NET  USB_INT              LOC="F5";    # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors
NET  usb_rstn             LOC="R11" | IOSTANDARD = LVCMOS33;   # Bank 12, Vcco=3.3V, DCI using 49.9 ohm resistors (USB_RESET_B)
NET  clk_100              LOC="AH15" | IOSTANDARD = LVCMOS33;  # Bank 4, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE0         LOC="AC4";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE1         LOC="AC5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE2         LOC="AB6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE3         LOC="AB7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE4         LOC="AA5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE5         LOC="AB5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE6         LOC="AC7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_BLUE7         LOC="AD7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_CLAMP         LOC="AH7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_COAST         LOC="AG7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_DATA_CLK      LOC="AH18";  # Bank 4, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN0        LOC="Y8";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN1        LOC="Y9";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN2        LOC="AD4";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN3        LOC="AD5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN4        LOC="AA6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN5        LOC="Y7";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN6        LOC="AD6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_GREEN7        LOC="AE6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_HSOUT         LOC="AE7";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_ODD_EVEN_B    LOC="W6";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED0          LOC="AG5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED1          LOC="AF5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED2          LOC="W7";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED3          LOC="V7";    # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED4          LOC="AH5";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED5          LOC="AG6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED6          LOC="Y11";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_RED7          LOC="W11";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_SOGOUT        LOC="AF6";   # Bank 18, Vcco=3.3V, No DCI
#NET  VGA_IN_VSOUT         LOC="Y6";    # Bank 18, Vcco=3.3V, No DCI
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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [boards/] [xilinx-ml507-xc5vfx70t/] [leon3mp.ucf] - Rev 2
