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https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Subversion Repositories mips_enhanced
[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-altera-ep3sl150/] [leon3mp.jdi] - Rev 2
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<sld_project_info>
<hub_info ir_width="8" node_count="1"/>
<node_info>
<node hpath="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst" instance_id="0" mfg_id="110" node_id="8" sld_node_info="0x406E00" version="0">
<parameters>
<parameter name="sld_mfg_id" type="dec" value="110"/>
<parameter name="sld_type_id" type="dec" value="8"/>
<parameter name="sld_version" type="dec" value="0"/>
<parameter name="sld_instance_index" type="dec" value="0"/>
<parameter name="sld_auto_instance_index" type="string" value="NO"/>
<parameter name="sld_ir_width" type="dec" value="8"/>
<parameter name="SLD_NODE_INFO" type="dec" value="4222464"/>
</parameters>
<inputs>
<port name="usr_tdo" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|tdo"/>
<port name="usr_ir_out[0]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[0]"/>
<port name="usr_ir_out[1]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[1]"/>
<port name="usr_ir_out[2]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[2]"/>
<port name="usr_ir_out[3]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[3]"/>
<port name="usr_ir_out[4]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[4]"/>
<port name="usr_ir_out[5]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[5]"/>
<port name="usr_ir_out[6]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[6]"/>
<port name="usr_ir_out[7]" source="ahbjtag:\ahbjtaggen0:ahbjtag0|tap:tap0|altera_tap:\alt:u0|sld_virtual_jtag:u0|sld_virtual_jtag_basic:sld_virtual_jtag_basic_inst|ir_out[7]"/>
<port name="raw_tck" source="sld_hub:sld_hub_inst"/>
<port name="raw_tms" source="sld_hub:sld_hub_inst"/>
<port name="tdi" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_tlr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_rti" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_sdrs" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_cdr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_sdr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_e1dr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_pdr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_e2dr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_udr" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_sirs" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_cir" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_sir" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_e1ir" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_pir" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_e2ir" source="sld_hub:sld_hub_inst"/>
<port name="jtag_state_uir" source="sld_hub:sld_hub_inst"/>
<port name="usr1" source="sld_hub:sld_hub_inst"/>
<port name="clrn" source="sld_hub:sld_hub_inst"/>
<port name="ena" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[0]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[1]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[2]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[3]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[4]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[5]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[6]" source="sld_hub:sld_hub_inst"/>
<port name="ir_in[7]" source="sld_hub:sld_hub_inst"/>
</inputs>
<outputs>
<port name="usr_tck"/>
<port name="usr_tdi"/>
<port name="usr_ir_in[0]"/>
<port name="usr_ir_in[1]"/>
<port name="usr_ir_in[2]"/>
<port name="usr_ir_in[3]"/>
<port name="usr_ir_in[4]"/>
<port name="usr_ir_in[5]"/>
<port name="usr_ir_in[6]"/>
<port name="usr_ir_in[7]"/>
<port name="usr_virtual_state_cdr"/>
<port name="usr_virtual_state_sdr"/>
<port name="usr_virtual_state_e1dr"/>
<port name="usr_virtual_state_pdr"/>
<port name="usr_virtual_state_e2dr"/>
<port name="usr_virtual_state_udr"/>
<port name="usr_virtual_state_cir"/>
<port name="usr_virtual_state_uir"/>
<port name="usr_tms"/>
<port name="usr_jtag_state_tlr"/>
<port name="usr_jtag_state_rti"/>
<port name="usr_jtag_state_sdrs"/>
<port name="usr_jtag_state_cdr"/>
<port name="usr_jtag_state_sdr"/>
<port name="usr_jtag_state_e1dr"/>
<port name="usr_jtag_state_pdr"/>
<port name="usr_jtag_state_e2dr"/>
<port name="usr_jtag_state_udr"/>
<port name="usr_jtag_state_sirs"/>
<port name="usr_jtag_state_cir"/>
<port name="usr_jtag_state_sir"/>
<port name="usr_jtag_state_e1ir"/>
<port name="usr_jtag_state_pir"/>
<port name="usr_jtag_state_e2ir"/>
<port name="usr_jtag_state_uir"/>
<port name="tdo"/>
<port name="ir_out[0]"/>
<port name="ir_out[1]"/>
<port name="ir_out[2]"/>
<port name="ir_out[3]"/>
<port name="ir_out[4]"/>
<port name="ir_out[5]"/>
<port name="ir_out[6]"/>
<port name="ir_out[7]"/>
</outputs>
</node>
</node_info>
</sld_project_info>