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<h3><span style="font-family: helvetica,arial,sans-serif;">LEON3MP
reference design for the GR-XS3C-1500 board<br>
</span></h3>
<h4 style="font-family: helvetica,arial,sans-serif;">Introduction</h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
LEON3MP is a generic reference
design for LEON3-based systems. This version is specially adapted for
the <a href="http://www.pender.ch/">GR-XC3S-1500 Spartan3 development board</a>, and contains the following
functionality:<br>
<br>
</span></small>
<table border="0" cellpadding="2" cellspacing="2" width="700">
<tbody>
<tr>
<td valign="top">
<ul><li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
4 LEON3 processor
cores with MP support</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
debug support unit (DSU)<br>
</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">8-bit
PROM controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit SDRAM controller<br>
</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Round-robin
AHB arbiter/controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">AHB/APB bridge with
plug&play support<br>
</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Multi-processor
interrupt controller</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">32-bit modular timer
unit</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">1 -
2 UARTs with FIFO<br>
</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">10/100 ethernet MAC</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">PS2 mouse/keyboard interface</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">24-bit Video DAC interface<br>
</span></small></li>
<li><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">Etherner debug
communication link</span></small></li><li><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug communication link</span></small></li></ul>
</td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"><img alt="" src="../../boards/gr-xc3s-1500/gr-xc3s_top_small.jpg" align="right" height="212" width="320"></span></small></td>
</tr>
</tbody>
</table>
<small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
<br>
The LEON3MP-GR-XS3C-1500 design is provided together with GRLIB, and is
located in grlib/designs/leon3-gr-xc3s-1500 .<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
</span></small>
<h4><span style="font-family: helvetica,arial,sans-serif;">Reference
architecture</span></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
LEON3MP is made up by cores from the GRLIB IP library, which are
connected together via the AMBA AHB and APB buses. The plug&play
configuration method of GRLIB makes it possible to assign any
combination of addresses and interrupts to the cores. However, to be
software compatible with simple operating systems such as the LEON
Bare-C cross-compiler, some of the vital cores must be assigned to
predefined addresses and interrupts. The table below shows the
reference assigment in the LEON3MP design:<br>
<br>
</span></small>
<table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
<tbody>
<tr>
<th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">PROM/SDRAM controller<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x00000000 -
0x20000000 : 8 Mbyte 8-bit flash PROM<br>
0x40000000 - 0x80000000 : 64 Mbyte 32-bit SDRAM<br>
0x80000000 - 0x80000100 : Configuration registers (APB)<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">APB bridge<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000000 -
0x80100000 : APB bus<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000100 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 : UART1
registers</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">2</span></small><br>
</td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt controller</span></small><br>
</td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000200 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300 : IRQ
registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Timer unit<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000300</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0x80000400 : timer
registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">8, 9<br>
</span></small></td>
</tr>
<tr>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">LEON3 debug support
unit (DSU)<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x90000000 -
0xA0000000 : DSU registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
</tbody>
</table>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
Additional (optional) IP cores are assigned addresses and interrupts as
desribed in the table below. These assignments are LEON3MP specific and
can be changed without impact on software compatibility.<br>
<br>
</span></small>
<table style="width: 100%; text-align: left;" border="1" cellpadding="2" cellspacing="2">
<tbody>
<tr>
<th style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Core</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Memory area<br>
</span></small></th>
<th style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">Interrupt</span></small></th>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Serial debug
communication link<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000700 - </span></small><small><span style="font-family: helvetica,arial,sans-serif;">0x80000800 : AHB UART
registers</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">Ethernet debug
communication link</span></small><br>
</td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small> </td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">JTAG debug
communication link</span></small></td>
<td valign="top">-<br>
</td>
<td valign="top">-<br>
</td>
</tr>
<tr>
<td style="vertical-align: top; width: 250px;"><small><span style="font-family: helvetica,arial,sans-serif;">10/100 Mbit ethernet MAC<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xFFFB0000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xFFFB1000 :
ethernet
control registers<br>
</span></small></td>
<td style="vertical-align: top;"><small><span style="font-family: helvetica,arial,sans-serif;">12</span></small></td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">On-chip RAM<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">0xA0000000</span></small><small><span style="font-family: helvetica,arial,sans-serif;"> -</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> 0xA0100000 : On-chip
RAM<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">UART</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000900 -
0x80000A00 : Secondary UART<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">3</span></small></td>
</tr><tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">PS/2 Keyboard interface</span></small><br>
</td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000500 -
0x80000600 : PS/2 registers<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">4</span></small><br>
</td>
</tr>
<tr>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">VGA controller<br>
</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">0x80000600 -
0x80000700 : VGA registers</span></small></td>
<td valign="top"><small><span style="font-family: helvetica,arial,sans-serif;">-</span></small></td>
</tr>
</tbody>
</table>
<br>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">
</span></small></h4>
<h4><span style="font-family: helvetica,arial,sans-serif;">Configuration</span></h4>
<div style="text-align: left;"><small><span style="font-family: helvetica,arial,sans-serif;">The configuartion of
the LEON3MP design is defined through the config package located <a href="config.vhd">config.vhd</a>.
This file can be automatically generated using a GUI based on tkconfig.
To launch the GUI, do 'make xconfig'. After the configuration is
completed, save and
exit the tool and config.vhd will be created automatically.<br>
<br>
<img alt="" src="../share/gui.gif" height="148" width="561"><br>
<br>
<i>Figure 1. LEON3MP configuration GUI</i></span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><br style="font-family: helvetica,arial,sans-serif;">
<small>
</small></div>
<h4><span style="font-family: helvetica,arial,sans-serif;">Simulation</span></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
simulate the testbench, first compile the model for simulation. This
can be done automatically for three different simulators. Execute one
of the following commands:</span><br style="font-family: helvetica,arial,sans-serif;">
</small>
<ul style="font-family: helvetica,arial,sans-serif;">
<li><small>make vsim</small></li><li><small>make ncsim</small></li><li><small>make ghdl</small></li>
</ul>
<small><span style="font-family: helvetica,arial,sans-serif;">For vsim,
start the simulation with 'vsim testbench' and do 'run 100'. This
should print the current LEON3MP configuration:</span><br style="font-family: helvetica,arial,sans-serif;">
</small><br>
<small><span style="font-family: courier new,courier,monospace;">$ vsim
-c -quiet testbench</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/usr/local/model58/tcl/vsim/pref.tcl</span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">Reading
/home/jiri/modelsim.tcl</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span></small><br style="font-family: courier new,courier,monospace;">
<small><span style="font-family: courier new,courier,monospace;"># 5.8</span><br style="font-family: courier new,courier,monospace;">
</small><small><span style="font-family: courier new,courier,monospace;"></span><big><tt>#
VSIM 1> run<br>
# LEON3 Demonstration design<br>
# GRLIB Version 0.13<br>
# Target technology: virtex2 , memory library: virtex2<br>
# ahbctrl: mst0: Gaisler
Research Leon3 SPARC V8
Processor<br>
# ahbctrl: mst1: Gaisler
Research AHB Debug UART<br>
# ahbctrl: mst2: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# ahbctrl: mst3: Gaisler
Research AMBA DMA controller<br>
# ahbctrl: mst5: Gaisler
Research OC ethernet AHB
interface<br>
# ahbctrl: slv0: Gaisler
Research Simple SRAM
Controller<br>
# ahbctrl: memory at 0x00000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl: memory at 0x40000000,
size 16 Mbyte, cacheable, prefetch<br>
# ahbctrl: slv1: Gaisler
Research AHB/APB Bridge<br>
# ahbctrl: memory at 0x80000000,
size 1 Mbyte<br>
# ahbctrl: slv2: Gaisler
Research Leon3 Debug Support
Unit<br>
# ahbctrl: memory at 0x90000000,
size 256 Mbyte<br>
# ahbctrl: slv4: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# ahbctrl: memory at 0xe0000000,
size 256 Mbyte<br>
# ahbctrl: I/O port at 0xfff80000,
size 128kbyte<br>
# ahbctrl: slv5: Gaisler
Research OC ethernet AHB
interface<br>
# ahbctrl: I/O port at 0xfffb0000,
size 4kbyte<br>
# ahbctrl: slv6: Gaisler
Research OC CAN AHB interface<br>
# ahbctrl: I/O port at 0xfffc0000,
size 4kbyte<br>
# ahbctrl: slv7: Gaisler
Research Generic AHB SRAM
module<br>
# ahbctrl: memory at 0xa0000000,
size 1 Mbyte, cacheable, prefetch<br>
# ahbctrl: AHB arbiter/multiplexer rev 1<br>
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte<br>
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte<br>
# apbctrl: APB Bridge at 0x80000000 rev 1<br>
# apbctrl: slv1: Gaisler
Research Generic UART<br>
# apbctrl: I/O ports at 0x80000100,
size 256 byte<br>
# apbctrl: slv2: Gaisler
Research Multi-processor
Interrupt Ctrl.<br>
# apbctrl: I/O ports at 0x80000200,
size 256 byte<br>
# apbctrl: slv3: Gaisler
Research Modular Timer Unit<br>
# apbctrl: I/O ports at 0x80000300,
size 256 byte<br>
# apbctrl: slv4: Gaisler
Research Fast 32-bit PCI
Bridge<br>
# apbctrl: I/O ports at 0x80000400,
size 256 byte<br>
# apbctrl: slv5: Gaisler
Research AMBA DMA controller<br>
# apbctrl: I/O ports at 0x80000500,
size 256 byte<br>
# apbctrl: slv7: Gaisler
Research AHB Debug UART<br>
# apbctrl: I/O ports at 0x80000700,
size 256 byte<br>
# ahbram7: AHB SRAM Module rev 1, 2 kbytes<br>
# can_oc6: Opencores CAN MAC, rev 0, irq 13<br>
# eth_oc5: Wishbone/AHB interface for OC ethernet MAC, irq 12<br>
# eth_oc5: Opencores 10/100 Mbit ethernet MAC, rev 0<br>
# pci_mtf4: 32-bit PCI/AHB bridge rev 0, 2 Mbyte PCI memory BAR,
8-word FIFOs<br>
# dmactrl5: 32-bit DMA controller & AHB/AHB bridge rev 0<br>
# gptimer3: GR Timer Unit rev 0, 16-bit scaler, 1 32-bit timers, irq 8<br>
# irqmp: Multi-processor Interrupt Controller rev 1, #cpu 1<br>
# apbuart1: Generic UART rev 1, irq 2<br>
# srctrl0: 32-bit PROM/SRAM controller rev 0<br>
# ahbuart7: AHB Debug UART rev 0<br>
# dsu3_2: LEON3 Debug support unit<br>
# leon3_0: LEON3 SPARC V8 processor rev 0<br>
# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte</tt></big><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;"></span><span style="font-family: courier new,courier,monospace;"></span><br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">VSIM 2>
run -all<br># **** GRLIB system test starting ****<br>
# Leon3 SPARC V8 Processor<br>
# register file<br>
# multiplier<br>
# radix-2 divider<br>
# cache system<br>
# Multi-processor Interrupt Ctrl.<br>
# Generic UART<br>
# Modular Timer Unit<br>
# Test passed, halting with IU error mode<br>
#<br>
# ** Failure: *** IU in error mode, simulation halted ***<br>
# Time: 669213500 ps Iteration: 1 Process: /testbench/iuerr File: testbench.vhd<br>
# Break at testbench.vhd line 263<br>
# Stopped at testbench.vhd line 263<br>
<br>
</span></small><h4><small><span style="font-family: helvetica,arial,sans-serif;">Synthesis<br>
</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
synthesize and place&route, use the make utility and issue either 'make ise' or 'make ise-synp' to<br>
use the XST or Synplify tools respectively.<br>
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;">Alternatively, the design can be implemented using
the graphical XGrlib tool, which is started with 'make xgrlib'.<br>
<br>
<br>
<img alt="" src="../../doc/grlib/xgrlib.gif" height="537" width="619"></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> </span></small><br>
<div style="text-align: justify;"><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></div>
<small><span style="font-family: helvetica,arial,sans-serif;">
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"><i>Figure 2. XGrlib
implementation tool</i></span></small><br>
<small><span style="font-family: helvetica,arial,sans-serif;"><br>
To program the fpga, issue 'make ise-prog-fpga'. To re-program the configuration proms, do 'make ise-prog-prom'.<br>
After programming the proms, power-cycle the board to re-load the fpga.<br>
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;">To get
started quicker, suitable leon3mp.bit and leon3mp.msk files are provided in the <i>bitfiles</i>
directory. The fpga or
configuration proms can be programmed directly with this configuration,
using the following commands: 'make ise-prog-fpga-ref' or 'make
ise-prog-prom-ref '.</span></small><br>
<small><span style="font-family: helvetica,arial,sans-serif;">
</span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">Software
development</span></small></h4>
<h4><small><span style="font-family: helvetica,arial,sans-serif;"></span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">To
develop RTEMS applications, download and install the <a href="http://www.gaisler.se/bin/linux/rcc-1.0.0.pdf">LEON3 RTEMS
Cross-compiler</a> from gaisler.com. The LEON3 bsp automatically
detects
the location of UARTs, timers, interrupt controller and ethernet core
using the plug&play information. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">
A <a href="http://www.gaisler.com/doc/bcc.html">LEON3 bare-C compiler</a>
is also available for download from gaisler.com. Both the RTEMS
and the bare-C compilers now come with full source code for both the
low-level I/O routines as well as the mkprom prom builder. This should
allow users to adapt the run-time to their own needs. All sources are
provided under GNU GPL, contact <a href="mailto:sales@gaisler.com">Gaisler
Research</a> for commercial licenses of this software.<br>
<br>
A Leon3 port of uClinux and linux-2.6.11 is available in the <a href="http://www.gaisler.com/products/linux.html">snapgear
linux distribution</a>.<br>
</span></small>
<h4><small><span style="font-family: helvetica,arial,sans-serif;">Debugging<br>
</span></small></h4>
<small><span style="font-family: helvetica,arial,sans-serif;">The
on-chip debug support unit (DSU) makes debugging of target hardware
relatively easy. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">The
design support both serial, ethernet and JTAG debug interface, and the </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> <a href="http://www.gaisler.com/products/grmon/grmon.html">GRMON debug
monitor</a></span></small><small><span style="font-family: helvetica,arial,sans-serif;"> can be attached with a serial cable, over a LAN, or using the Xilinx JTAG programming cable. </span></small><small><span style="font-family: helvetica,arial,sans-serif;"> Note that when you use the ethernet or the JTAG
interface, you need specify the frequency of the AHB clock since it is
not auto-detected. </span></small><small><span style="font-family: helvetica,arial,sans-serif;">Below
is a log from a debug session.<br>
<br>
</span></small><small><span style="font-family: helvetica,arial,sans-serif;"></span></small><small><span style="font-family: helvetica,arial,sans-serif;">
<br style="font-family: courier new,courier,monospace;">
<span style="font-family: courier new,courier,monospace;">$jiri@home:~$ grmon -u -grlib -jtag -freq 40<br>
<br>
GRMON - The LEON multi purpose monitor v1.0.9<br>
<br>
Copyright (C) 2004, Gaisler Research - all rights reserved.<br>
For latest updates, go to http://www.gaisler.com/<br>
Comments or bug-reports to grmon@gaisler.com<br>
<br>
<br>
GRLIB DSU Monitor backend 1.0.2 (professional version)<br>
<br>
using JTAG cable on parallel port<br>
<br>
initialising .............<br>
<br> Component
Vendor<br>
Leon3 SPARC V8 Processor Gaisler Research<br>
AHB Debug
UART
Gaisler Research<br>
AHB Debug JTAG
TAP
Gaisler Research<br>
AHB interface for 10/100 Mbit MA Gaisler Research<br>
Nuhorizons Spartan3 I/O interfac Gaisler Research<br>
AHB/APB
Bridge
Gaisler Research<br>
Leon3 Debug Support Unit Gaisler Research<br>
32-bit PC133 SDRAM Controller Gaisler Research<br>
AHB interface for 10/100 Mbit MA Gaisler Research<br>
CAN
controller
Gaisler Research<br>
Generic APB
UART
Gaisler Research<br>
Multi-processor Interrupt Ctrl Gaisler Research<br>
Modular Timer
Unit
Gaisler Research<br>
<br>
Use command 'info sys' to print a detailed report of attached cores<br>
<br>
grmon[grlib]> inf sys<br>
00.01:003 Gaisler Research Leon3 SPARC V8 Processor (ver 0)<br>
ahb master 0<br>
01.01:007 Gaisler Research AHB Debug UART (ver 0)<br>
ahb master 1<br>
apb: 80000700 - 80000800<br>
baud rate 115200, ahb frequency 40.00<br>
02.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0)<br>
ahb master 2<br>
03.01:005 Gaisler Research AHB interface for 10/100 Mbit MA (ver 0)<br>
ahb master 3<br>
00.01:02b Gaisler Research Nuhorizons Spartan3 I/O interfac (ver 0)<br>
ahb: 00000000 - 00400000<br>
16-bit prom @ 0x00000000<br>
01.01:006 Gaisler Research AHB/APB Bridge (ver 0)<br>
ahb: 80000000 - 80100000<br>
02.01:004 Gaisler Research Leon3 Debug Support Unit (ver 0)<br>
ahb: 90000000 - a0000000<br>
AHB trace 64 lines, stack pointer 0x00000000<br>
CPU#0 win 8, hwbp 4, itrace 64, V8 mul/div, lddel 1<br>
icache 2 * 4 kbyte, 32 byte/line lru<br>
dcache 2 * 4 kbyte, 32 byte/line lru<br>
03.01:009 Gaisler Research 32-bit PC133 SDRAM Controller (ver 0)<br>
ahb: 40000000 - 48000000<br>
ahb: fff00100 - fff00200<br>
32-bit sdram: 1 * 16 Mbyte @ 0x40000000, col 8, cas 2, ref 15.6 us<br>
05.01:005 Gaisler Research AHB interface for 10/100 Mbit MA (ver 0)<br>
irq 12<br>
ahb: fffb0000 - fffb1000<br>
06.01:019 Gaisler Research CAN controller (ver 0)<br>
irq 13<br>
ahb: fffc0000 - fffc1000<br>
01.01:00c Gaisler Research Generic APB UART (ver 1)<br>
irq 2<br>
apb: 80000100 - 80000200<br>
baud rate 38400, DSU mode<br>
02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 2)<br>
apb: 80000200 - 80000300<br>
03.01:011 Gaisler Research Modular Timer Unit (ver 0)<br>
irq 8<br>
apb: 80000300 - 80000400<br>
8-bit scaler, 2 * 32-bit timers, divisor 40<br>
grmon[grlib]> lo /opt/sparc-elf/src/examples/stanford<br>
section: .text at 0x40000000, size 61200 bytes<br>
section: .data at 0x4000ef10, size 2080 bytes<br>
total size: 63280 bytes (222.1 kbit/s)<br>
read 197 symbols<br>
entry point: 0x40000000<br>
grmon[grlib]> run<br>
Starting<br>
Perm Towers Queens
Intmm Mm Puzzle
Quick Bubble Tree FFT<br>
34
50 34
34 900
316 34
50 217 1083<br>
<br>
Nonfloating point composite is 114<br>
<br>
Floating point composite is 857<br>
<br>
Program exited normally.<br>
grmon[grlib]></span><span style="font-family: courier new,courier,monospace;"></span><br>
<br>
<br>
The LEON3MP test bench includes memory models of both boot-prom, sram
and sdram. To build memory images for these models, do 'make soft' .
Note: this will require that the bare-C compiler for LEON3 is
installed,
and /opt/sparc-elf/bin is added to the PATH.<br>
<br>
<br>
</span></small></td>
</tr>
<tr>
<td valign="top"><br>
</td>
</tr>
</tbody>
</table>
<h3><br>
<span style="font-family: helvetica,arial,sans-serif;"></span></h3>
<small><span style="font-family: helvetica,arial,sans-serif;">
</span></small>
</body></html>