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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [lib/] [gaisler/] [spacewire/] [spacewire.in.help] - Rev 2
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Spacewire link
CONFIG_SPW_ENABLE
Say Y here to enable one or more Spacewire serial links. The links
are based on the GRSPW core from Gaisler Research.
Number of spacewire links
CONFIG_SPW_NUM
Select the number of links to implement. Each link will be a
separate AHB master and APB slave for configuration.
AHB FIFO depth
CONFIG_SPW_AHBFIFO4
Select the AHB FIFO depth (in 32-bit words).
RX FIFO depth
CONFIG_SPW_RXFIFO16
Select the receiver FIFO depth (in bytes).
RMAP protocol
CONFIG_SPW_RMAP
Enable hardware support for the RMAP protocol (draft C).
RMAP Buffer depth
CONFIG_SPW_RMAPBUF2
Select the size of the RMAP buffer (in bytes).
RMAP CRC
CONFIG_SPW_RMAPCRC
Enable hardware calculation of the RMAP CRC checksum
Netlists
CONFIG_SPW_NETLIST
Use the netlist version of GRSPWC. This option is required if
you have not licensed the source code of the Spacewire core.
Currently only supported for Virtex and Axcelerator FPGAs.
The AHB/RX FIFO sizes should be set to 16 word/byte, and the
RMAP should be disabled.
Spacewire FT
CONFIG_SPW_FT
Say Y here to implement the Spacewire block rams with fault-tolerance
against SEU errors.
Spacewire core
CONFIG_SPW_GRSPW1
Select to use GRSPW1 core or GRSPW2 core.