Subversion Repositories myblaze

--------------------------------------------------------------------------------
Release 10.1.03 Trace  (lin64)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

/home/daniel/Applications/Xilinx/10.1/ISE/bin/lin64/unwrapped/trce -ise
/home/daniel/Sources/myblaze/system/uart_test_top/uart_test_top.ise -intstyle
ise -v 3 -s 4 -xml SysTop SysTop.ncd -o SysTop.twr SysTop.pcf -ucf
/home/daniel/Sources/myblaze/rtl/uart_test_top.ucf

Design file:              SysTop.ncd
Physical constraint file: SysTop.pcf
Device,package,speed:     xc3s500e,fg320,-4 (PRODUCTION 1.27 2008-01-09)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_clock = PERIOD TIMEGRP "clock" 20 ns HIGH 50%;

 247273 paths analyzed, 1947 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is  17.967ns.
--------------------------------------------------------------------------------
Slack:                  2.033ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Mram_dmem_bank_3_ram.B (RAM)
  Destination:          core_exeu_ex_r_carry (FF)
  Requirement:          20.000ns
  Data Path Delay:      17.967ns (Levels of Logic = 22)
  Clock Path Skew:      0.000ns
  Source Clock:         clock_BUFGP rising at 0.000ns
  Destination Clock:    clock_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_carry
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
                                                       Mram_dmem_bank_3_ram.B
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
    SLICE_X54Y45.X       Tilo                  0.759   N274
                                                       core_deco_wb_dat_d<2>17_SW0
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>17
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>38
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
    SLICE_X27Y50.X       Tif5x                 1.025   N342
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
    SLICE_X43Y56.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
    SLICE_X43Y56.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<23>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
    SLICE_X43Y57.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
    SLICE_X43Y57.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<25>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
    SLICE_X43Y58.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
    SLICE_X43Y58.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<27>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
    SLICE_X43Y59.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
    SLICE_X43Y59.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<29>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>
    SLICE_X43Y60.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<31>
    SLICE_X43Y60.XB      Tcinxb                0.404   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<31>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<32>
    SLICE_X36Y53.F1      net (fanout=1)        1.072   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<32>
    SLICE_X36Y53.CLK     Tfck                  0.892   core_exeu_ex_r_carry
                                                       _old_SYSTOP_CORE_EXEU_COMB_r_carry_57
                                                       core_exeu_ex_r_carry
    -------------------------------------------------  ---------------------------
    Total                                     17.967ns (10.767ns logic, 7.200ns route)
                                                       (59.9% logic, 40.1% route)

--------------------------------------------------------------------------------
Slack:                  2.160ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Mram_dmem_bank_3_ram.B (RAM)
  Destination:          core_exeu_ex_r_alu_result_30 (FF)
  Requirement:          20.000ns
  Data Path Delay:      17.828ns (Levels of Logic = 21)
  Clock Path Skew:      -0.012ns (0.075 - 0.087)
  Source Clock:         clock_BUFGP rising at 0.000ns
  Destination Clock:    clock_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_alu_result_30
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
                                                       Mram_dmem_bank_3_ram.B
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
    SLICE_X54Y45.X       Tilo                  0.759   N274
                                                       core_deco_wb_dat_d<2>17_SW0
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>17
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>38
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
    SLICE_X27Y50.X       Tif5x                 1.025   N342
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
    SLICE_X43Y56.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<23>
    SLICE_X43Y56.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<23>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<24>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
    SLICE_X43Y57.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<25>
    SLICE_X43Y57.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<25>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<26>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
    SLICE_X43Y58.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<27>
    SLICE_X43Y58.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<27>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<28>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
    SLICE_X43Y59.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<29>
    SLICE_X43Y59.Y       Tciny                 0.869   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<29>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<30>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<31>
    SLICE_X40Y62.F3      net (fanout=1)        0.586   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<30>
    SLICE_X40Y62.CLK     Tfck                  0.892   core_exeu_ex_r_alu_result<30>
                                                       _old_SYSTOP_CORE_EXEU_COMB_result_53<30>63
                                                       core_exeu_ex_r_alu_result_30
    -------------------------------------------------  ---------------------------
    Total                                     17.828ns (11.114ns logic, 6.714ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------
Slack:                  2.225ns (requirement - (data path - clock path skew + uncertainty))
  Source:               Mram_dmem_bank_3_ram.B (RAM)
  Destination:          core_exeu_ex_r_alu_result_22 (FF)
  Requirement:          20.000ns
  Data Path Delay:      17.753ns (Levels of Logic = 17)
  Clock Path Skew:      -0.022ns (0.065 - 0.087)
  Source Clock:         clock_BUFGP rising at 0.000ns
  Destination Clock:    clock_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: Mram_dmem_bank_3_ram.B to core_exeu_ex_r_alu_result_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y6.DOB2     Tbcko                 2.812   Mram_dmem_bank_3_ram
                                                       Mram_dmem_bank_3_ram.B
    SLICE_X54Y45.F1      net (fanout=3)        1.099   dmem_bank_out<3><2>
    SLICE_X54Y45.X       Tilo                  0.759   N274
                                                       core_deco_wb_dat_d<2>17_SW0
    SLICE_X54Y44.G1      net (fanout=1)        0.438   N274
    SLICE_X54Y44.Y       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>17
    SLICE_X54Y44.F4      net (fanout=1)        0.023   core_deco_wb_dat_d<2>17/O
    SLICE_X54Y44.X       Tilo                  0.759   core_of_fwd_mem_result<2>
                                                       core_deco_wb_dat_d<2>38
    SLICE_X27Y50.F2      net (fanout=10)       2.532   SYSTOP_CORE_EXEU_COMB_MYHDL43_align_mem_store_1_MYHDL43_align_mem_store<2>
    SLICE_X27Y50.X       Tif5x                 1.025   N342
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0_G
                                                       Mmux__old_SYSTOP_CORE_EXEU_COMB_dat_b_432324_SW0
    SLICE_X39Y48.F1      net (fanout=1)        1.092   N342
    SLICE_X39Y48.X       Tilo                  0.704   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
                                                       _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.G2      net (fanout=3)        0.944   _old_SYSTOP_CORE_EXEU_COMB_alu_src_b_45<2>
    SLICE_X43Y45.COUT    Topcyg                1.001   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<1>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_lut<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<3>
    SLICE_X43Y46.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<3>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<4>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<5>
    SLICE_X43Y47.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<5>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<6>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<7>
    SLICE_X43Y48.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<7>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<8>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<9>
    SLICE_X43Y49.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<9>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<10>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<11>
    SLICE_X43Y50.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<11>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<12>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<13>
    SLICE_X43Y51.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<13>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<14>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<15>
    SLICE_X43Y52.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<15>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<16>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<17>
    SLICE_X43Y53.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<17>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<18>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<19>
    SLICE_X43Y54.COUT    Tbyp                  0.118   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<19>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<20>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.CIN     net (fanout=1)        0.000   Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<21>
    SLICE_X43Y55.Y       Tciny                 0.869   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<21>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_cy<22>
                                                       Madd__old_SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_cc_49_xor<23>
    SLICE_X44Y60.F2      net (fanout=1)        0.983   SYSTOP_CORE_EXEU_COMB_MYHDL45_add_1_MYHDL45_add<22>
    SLICE_X44Y60.CLK     Tfck                  0.892   core_exeu_ex_r_alu_result<22>
                                                       _old_SYSTOP_CORE_EXEU_COMB_result_53<22>63
                                                       core_exeu_ex_r_alu_result_22
    -------------------------------------------------  ---------------------------
    Total                                     17.753ns (10.642ns logic, 7.111ns route)
                                                       (59.9% logic, 40.1% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |   17.967|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 247273 paths, 0 nets, and 5595 connections

Design statistics:
   Minimum period:  17.967ns{1}   (Maximum frequency:  55.658MHz)


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sun Nov 21 23:39:25 2010 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 248 MB