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-- ------------------------------------------------------------------------
-- Copyright (C) 2010 Arif Endro Nugroho
-- All rights reserved.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity xtime_2 is
port (
  x2i : in  bit_vector (07 downto 00);
  x2o : out bit_vector (07 downto 00)
);
end xtime_2;
 
architecture phy of xtime_2 is
begin
	x2o <= (  x2i(06 downto 04) & ( x2i(03 downto 02) xor ( x2i(07) & x2i(07) ) ) &  x2i(01) & ( x2i(00) xor x2i(07) ) &  x2i(07) );
end phy;