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-- Copyright (C) 2010 Arif Endro Nugroho
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity c4b is
  port (
  cnt : out bit_vector (03 downto 00);
  clk : in  bit;
  rst : in  bit
  );
end c4b;
 
architecture phy of c4b is
  signal sum : bit_vector (03 downto 00) := B"1111"; -- sum
  signal cr  : bit_vector (03 downto 00) := B"0000"; -- carry
  begin
    cr(0)            <= '0'; -- LSB always zero
    cr(03 downto 01) <= ( ((sum(02 downto 00) and B"001") or (sum(02 downto 00) and cr(02 downto 00))) or (B"001" and cr(02 downto 00)) );
    process (clk)
    begin
      if (clk = '1' and clk'event) then
        if (rst = '1') then
          sum <= B"0001"; -- we start counting from 1
        else
          sum <= ((sum xor B"0001") xor cr); -- sum = ((addend xor augend) xor carry)
        end if;
      end if;
    end process;
    cnt <= sum;
end phy;